Lines Matching refs:rate
237 long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
241 rate = params_rate(params);
245 dev_dbg(spdif->dev, "hw_params rate %ld channels %u format %u\n",
246 rate, channels, format);
254 pre_div_a = clk_round_rate(spdif->clk_ref, rate * 256);
257 pre_div_b = clk_round_rate(spdif->clk_ref, rate * 384);
261 diff_a = abs((pre_div_a / 256) - rate);
262 diff_b = abs((pre_div_b / 384) - rate);
264 /* If diffs are equal, use lower clock rate */
272 * change. Get the current rate and set the register bit according to
277 diff_a = abs((clk_rate / 256) - rate);
278 diff_b = abs((clk_rate / 384) - rate);