Lines Matching refs:ret
634 int ret;
636 ret = clk_prepare_enable(ssi->clk);
637 if (ret)
638 return ret;
689 int ret;
776 ret = clk_set_rate(ssi->baudclk, baudrate);
777 if (ret) {
810 int ret;
813 ret = fsl_ssi_set_bclk(substream, dai, hw_params);
814 if (ret)
815 return ret;
819 ret = clk_prepare_enable(ssi->baudclk);
820 if (ret)
821 return ret;
1189 int ret;
1196 ret = clk_prepare_enable(fsl_ac97_data->clk);
1197 if (ret) {
1199 ret);
1226 int ret;
1230 ret = clk_prepare_enable(fsl_ac97_data->clk);
1231 if (ret) {
1232 pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
1323 int ret;
1331 ret = PTR_ERR(ssi->clk);
1332 dev_err(dev, "failed to get clock: %d\n", ret);
1333 return ret;
1338 ret = clk_prepare_enable(ssi->clk);
1339 if (ret) {
1340 dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
1341 return ret;
1372 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
1373 if (ret)
1376 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1377 if (ret)
1387 return ret;
1406 int ret;
1414 ret = of_property_match_string(np, "clock-names", "ipg");
1416 ssi->has_ipg_clk_name = ret >= 0;
1423 ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
1424 if (ret) {
1453 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1454 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
1490 int ret = 0;
1499 ret = fsl_ssi_probe_from_dt(ssi);
1500 if (ret)
1501 return ret;
1577 ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
1578 if (ret)
1579 return ret;
1584 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1585 if (ret) {
1591 ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
1593 if (ret) {
1594 dev_err(dev, "failed to register DAI: %d\n", ret);
1599 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
1601 if (ret < 0) {
1627 ret = PTR_ERR(ssi->card_pdev);
1629 ssi->card_name, ret);
1648 return ret;