Lines Matching refs:TX
54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
56 #define TX 1
211 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
214 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
221 * @regvals: Specific RX/TX register settings
241 * @fifo_watermark or fewer words in TX fifo or
402 int dir = tx ? TX : RX;
422 srcr = vals[RX].srcr | vals[TX].srcr;
423 stcr = vals[RX].stcr | vals[TX].stcr;
424 sier = vals[RX].sier | vals[TX].sier;
448 /* Enable SSI first to send TX DMA request */
452 /* Busy wait until TX FIFO not empty -- DMA working */
461 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
506 int adir = tx ? RX : TX;
507 int dir = tx ? TX : RX;
588 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
589 vals[TX].stcr = SSI_STCR_TFEN0;
590 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
594 vals[RX].scr = vals[TX].scr = 0;
598 vals[TX].stcr |= SSI_STCR_TFEN1;
603 vals[TX].sier |= SSI_SIER_TDMAE;
606 vals[TX].sier |= SSI_SIER_TIE;
795 * running in synchronous mode (both TX and RX use STCCR), it is not
1025 * @tx_mask: mask for TX
1096 * To be safe, configure SACCST right before TX starts.
1548 * Configure TX and RX DMA watermarks -- when to send a DMA request
1556 * Set to 8 as a balanced configuration -- When TX FIFO has 8
1559 * transaction before TX FIFO underruns; Same applies to RX.