Lines Matching refs:RX
54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
55 #define RX 0
211 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
214 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
221 * @regvals: Specific RX/TX register settings
242 * @fifo_watermark or more empty words in RX fifo.
402 int dir = tx ? TX : RX;
422 srcr = vals[RX].srcr | vals[TX].srcr;
423 stcr = vals[RX].stcr | vals[TX].stcr;
424 sier = vals[RX].sier | vals[TX].sier;
506 int adir = tx ? RX : TX;
507 int dir = tx ? TX : RX;
585 vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
586 vals[RX].srcr = SSI_SRCR_RFEN0;
587 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
594 vals[RX].scr = vals[TX].scr = 0;
597 vals[RX].srcr |= SSI_SRCR_RFEN1;
602 vals[RX].sier |= SSI_SIER_RDMAE;
605 vals[RX].sier |= SSI_SIER_RIE;
771 /* STCCR is used for RX in synchronous mode */
795 * running in synchronous mode (both TX and RX use STCCR), it is not
1026 * @rx_mask: mask for RX
1431 * In synchronous mode, STCK and STFS ports are used by RX
1548 * Configure TX and RX DMA watermarks -- when to send a DMA request
1559 * transaction before TX FIFO underruns; Same applies to RX.