Lines Matching refs:ret
173 int ret;
175 ret = regmap_update_bits(micfil->regmap,
179 if (ret) {
180 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
181 return ret;
184 ret = regmap_update_bits(micfil->regmap,
188 if (ret) {
189 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
190 return ret;
199 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
201 if (ret)
202 return ret;
208 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
209 if (ret)
210 return ret;
219 int ret;
223 ret = clk_set_rate(micfil->mclk, freq * 1024);
224 if (ret)
226 freq * 1024, ret);
230 return ret;
251 int ret;
257 ret = fsl_micfil_reset(dev);
258 if (ret) {
260 return ret;
269 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
272 if (ret) {
274 return ret;
278 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
281 if (ret) {
283 return ret;
291 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
294 if (ret) {
296 return ret;
299 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
302 if (ret) {
304 return ret;
317 int ret;
319 ret = fsl_micfil_set_mclk_rate(micfil, rate);
320 if (ret < 0)
325 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
328 if (ret)
335 ret = -EINVAL;
337 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
339 if (ret)
343 return ret;
354 int ret;
357 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
359 if (ret) {
361 return ret;
365 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
367 if (ret) {
368 dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
370 return ret;
373 ret = fsl_set_clock_params(dev, rate);
374 if (ret < 0) {
375 dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
376 return ret;
390 int ret;
395 ret = fsl_micfil_set_mclk_rate(micfil, freq);
396 if (ret < 0)
400 return ret;
415 int ret;
419 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
421 if (ret) {
424 return ret;
437 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
440 if (ret) {
442 return ret;
663 int ret, i;
706 ret = of_property_read_u32_index(np,
710 if (ret)
731 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
734 if (ret) {
737 return ret;
741 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
744 if (ret) {
747 return ret;
759 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
761 if (ret) {
764 return ret;
767 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
768 if (ret)
771 return ret;
788 int ret;
790 ret = clk_prepare_enable(micfil->mclk);
791 if (ret < 0)
792 return ret;