Lines Matching refs:esai_priv
105 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
106 struct platform_device *pdev = esai_priv->pdev;
110 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
111 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
114 esai_priv->soc->reset_at_xrun) {
116 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
118 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
120 schedule_work(&esai_priv->work);
173 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
239 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
248 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
267 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
268 struct clk *clksrc = esai_priv->extalclk;
269 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);
282 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
286 esai_priv->sck_div[tx] = true;
289 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
298 clksrc = esai_priv->fsysclk;
304 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
333 if (ratio == 1 && clksrc == esai_priv->extalclk) {
348 esai_priv->sck_div[tx] = false;
351 esai_priv->hck_dir[tx] = dir;
352 esai_priv->hck_rate[tx] = freq;
354 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
369 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
370 u32 hck_rate = esai_priv->hck_rate[tx];
375 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
393 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
399 esai_priv->sck_div[tx] ? 0 : ratio);
404 esai_priv->sck_rate[tx] = freq;
412 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
414 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
417 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
420 esai_priv->slot_width = slot_width;
421 esai_priv->slots = slots;
422 esai_priv->tx_mask = tx_mask;
423 esai_priv->rx_mask = rx_mask;
430 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
484 esai_priv->slave_mode = false;
489 esai_priv->slave_mode = true;
505 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
506 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
510 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
511 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
519 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
523 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
524 ESAI_SAICR_SYNC, esai_priv->synchronous ?
528 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
530 ESAI_xCCR_xDC(esai_priv->slots));
531 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
533 ESAI_xCCR_xDC(esai_priv->slots));
544 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
548 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
554 if (esai_priv->slot_width)
555 slot_width = esai_priv->slot_width;
557 bclk = params_rate(params) * slot_width * esai_priv->slots;
559 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);
566 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
568 if (!tx && esai_priv->synchronous)
569 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);
572 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
576 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
581 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
584 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
587 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
591 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
593 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
598 static int fsl_esai_hw_init(struct fsl_esai *esai_priv)
600 struct platform_device *pdev = esai_priv->pdev;
604 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
616 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
624 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
626 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
632 static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
637 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
639 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
642 regcache_mark_dirty(esai_priv->regmap);
643 ret = regcache_sync(esai_priv->regmap);
648 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
649 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
654 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
656 u8 i, channels = esai_priv->channels[tx];
657 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
660 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
665 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
679 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
682 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
684 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
686 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
690 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
694 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
696 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
699 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
701 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
703 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
707 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
709 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
715 struct fsl_esai *esai_priv = container_of(work, struct fsl_esai, work);
720 spin_lock_irqsave(&esai_priv->lock, lock_flags);
722 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);
723 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
728 fsl_esai_trigger_stop(esai_priv, tx);
729 fsl_esai_trigger_stop(esai_priv, rx);
732 fsl_esai_hw_init(esai_priv);
735 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
737 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
741 fsl_esai_register_restore(esai_priv);
744 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
746 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
748 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
750 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
755 fsl_esai_trigger_start(esai_priv, tx);
757 fsl_esai_trigger_start(esai_priv, rx);
759 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
765 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
769 esai_priv->channels[tx] = substream->runtime->channels;
775 spin_lock_irqsave(&esai_priv->lock, lock_flags);
776 fsl_esai_trigger_start(esai_priv, tx);
777 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
782 spin_lock_irqsave(&esai_priv->lock, lock_flags);
783 fsl_esai_trigger_stop(esai_priv, tx);
784 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
804 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
806 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
807 &esai_priv->dma_params_rx);
958 struct fsl_esai *esai_priv;
964 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
965 if (!esai_priv)
968 esai_priv->pdev = pdev;
969 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
971 esai_priv->soc = of_device_get_match_data(&pdev->dev);
972 if (!esai_priv->soc) {
983 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
985 if (IS_ERR(esai_priv->regmap)) {
987 PTR_ERR(esai_priv->regmap));
988 return PTR_ERR(esai_priv->regmap);
991 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
992 if (IS_ERR(esai_priv->coreclk)) {
994 PTR_ERR(esai_priv->coreclk));
995 return PTR_ERR(esai_priv->coreclk);
998 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
999 if (IS_ERR(esai_priv->extalclk))
1001 PTR_ERR(esai_priv->extalclk));
1003 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
1004 if (IS_ERR(esai_priv->fsysclk))
1006 PTR_ERR(esai_priv->fsysclk));
1008 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1009 if (IS_ERR(esai_priv->spbaclk))
1011 PTR_ERR(esai_priv->spbaclk));
1018 esai_priv->name, esai_priv);
1025 esai_priv->slots = 2;
1028 esai_priv->slave_mode = true;
1033 esai_priv->fifo_depth = be32_to_cpup(iprop);
1035 esai_priv->fifo_depth = 64;
1037 esai_priv->dma_params_tx.maxburst = 16;
1038 esai_priv->dma_params_rx.maxburst = 16;
1039 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
1040 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
1042 esai_priv->synchronous =
1046 if (esai_priv->synchronous) {
1052 dev_set_drvdata(&pdev->dev, esai_priv);
1054 spin_lock_init(&esai_priv->lock);
1055 ret = fsl_esai_hw_init(esai_priv);
1059 esai_priv->tx_mask = 0xFFFFFFFF;
1060 esai_priv->rx_mask = 0xFFFFFFFF;
1063 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
1064 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
1065 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
1066 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
1075 INIT_WORK(&esai_priv->work, fsl_esai_hw_reset);
1079 regcache_cache_only(esai_priv->regmap, true);
1090 struct fsl_esai *esai_priv = platform_get_drvdata(pdev);
1093 cancel_work_sync(&esai_priv->work);