Lines Matching defs:easrc
50 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
51 struct fsl_easrc_priv *easrc_priv = easrc->private;
65 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
66 struct fsl_easrc_priv *easrc_priv = easrc->private;
174 struct fsl_asrc *easrc = ctx->asrc;
175 struct fsl_easrc_priv *easrc_priv = easrc->private;
205 dev_err(&easrc->pdev->dev, "ratio exceed range\n");
209 regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index),
211 regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index),
239 static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc,
245 if (!easrc)
248 dev = &easrc->pdev->dev;
278 regmap_update_bits(easrc->regmap, reg, mask, 0);
279 regmap_update_bits(easrc->regmap, reg, mask, val);
280 regmap_update_bits(easrc->regmap, reg, mask, 0);
299 static int fsl_easrc_resampler_config(struct fsl_asrc *easrc)
301 struct device *dev = &easrc->pdev->dev;
302 struct fsl_easrc_priv *easrc_priv = easrc->private;
342 regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0]));
343 regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1]));
352 regmap_update_bits(easrc->regmap, REG_EASRC_CRCC,
357 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM);
373 regmap_write(easrc->regmap, REG_EASRC_CRCM,
375 regmap_write(easrc->regmap, REG_EASRC_CRCM,
389 * @easrc: Structure pointer of fsl_asrc
395 static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc,
400 struct device *dev = &easrc->pdev->dev;
428 static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id,
431 struct device *dev = &easrc->pdev->dev;
450 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM);
455 ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift);
460 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
462 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
469 static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc,
483 if (!easrc)
486 dev = &easrc->pdev->dev;
493 easrc_priv = easrc->private;
495 ctx = easrc->pair[ctx_id];
509 regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0);
510 regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0);
553 regmap_update_bits(easrc->regmap,
636 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
647 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
652 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
656 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
671 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
678 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
682 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
687 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
692 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
696 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
750 struct fsl_asrc *easrc = ctx->asrc;
782 regmap_update_bits(easrc->regmap, reg0,
786 regmap_update_bits(easrc->regmap, reg0,
790 regmap_update_bits(easrc->regmap, reg0,
794 regmap_update_bits(easrc->regmap, reg0,
807 regmap_update_bits(easrc->regmap, reg2,
816 regmap_update_bits(easrc->regmap, reg2,
824 regmap_update_bits(easrc->regmap, reg1,
830 regmap_update_bits(easrc->regmap, reg3,
839 regmap_update_bits(easrc->regmap, reg3,
844 regmap_update_bits(easrc->regmap, reg0,
861 static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
863 struct fsl_easrc_priv *easrc_priv = easrc->private;
864 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
912 dev_err(&easrc->pdev->dev, "no avail slot.\n");
924 static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
926 struct fsl_easrc_priv *easrc_priv = easrc->private;
927 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
937 regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0);
938 regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0);
939 regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0);
940 regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0);
949 regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0);
950 regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0);
951 regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0);
952 regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0);
964 static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id)
972 if (!easrc)
975 dev = &easrc->pdev->dev;
982 ctx = easrc->pair[ctx_id];
993 ret = fsl_easrc_prefilter_config(easrc, ctx->index);
997 spin_lock_irqsave(&easrc->lock, lock_flags);
998 ret = fsl_easrc_config_slot(easrc, ctx->index);
999 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1010 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
1014 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
1022 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
1031 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id),
1036 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
1046 struct fsl_asrc *easrc = ctx->asrc;
1047 struct fsl_easrc_priv *easrc_priv = easrc->private;
1129 struct fsl_asrc *easrc = ctx->asrc;
1142 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1145 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1148 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1151 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1156 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1167 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1170 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1173 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1176 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1181 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1185 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1201 struct fsl_asrc *easrc;
1206 easrc = ctx->asrc;
1210 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1213 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1216 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1221 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1224 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1227 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1243 struct fsl_asrc *easrc = ctx->asrc;
1249 dev = &easrc->pdev->dev;
1251 spin_lock_irqsave(&easrc->lock, lock_flags);
1254 if (easrc->pair[i])
1264 } else if (channels > easrc->channel_avail) {
1271 easrc->pair[index] = ctx;
1272 easrc->channel_avail -= channels;
1275 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1288 struct fsl_asrc *easrc;
1293 easrc = ctx->asrc;
1295 spin_lock_irqsave(&easrc->lock, lock_flags);
1297 fsl_easrc_release_slot(easrc, ctx->index);
1299 easrc->channel_avail += ctx->channels;
1300 easrc->pair[ctx->index] = NULL;
1302 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1312 struct fsl_asrc *easrc = ctx->asrc;
1314 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1316 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1318 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1330 struct fsl_asrc *easrc = ctx->asrc;
1335 regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val);
1338 regmap_update_bits(easrc->regmap,
1342 regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val);
1348 regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val);
1350 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
1353 regmap_write_bits(easrc->regmap,
1363 dev_warn(&easrc->pdev->dev, "RUN STOP fail\n");
1366 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1368 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1370 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1378 struct fsl_asrc *easrc = ctx->asrc;
1385 return dma_request_slave_channel(&easrc->pdev->dev, name);
1442 struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai);
1444 struct device *dev = &easrc->pdev->dev;
1467 ctx_priv->out_params.sample_rate = easrc->asrc_rate;
1468 ctx_priv->out_params.sample_format = easrc->asrc_format;
1472 ctx_priv->in_params.sample_rate = easrc->asrc_rate;
1473 ctx_priv->in_params.sample_format = easrc->asrc_format;
1492 ret = fsl_easrc_config_context(easrc, ctx->index);
1543 struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev);
1546 &easrc->dma_params_tx,
1547 &easrc->dma_params_rx);
1576 .name = "fsl-easrc-dai",
1754 static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc)
1756 struct fsl_easrc_priv *easrc_priv = easrc->private;
1760 struct device *dev = &easrc->pdev->dev;
1799 static int fsl_easrc_get_firmware(struct fsl_asrc *easrc)
1807 if (!easrc)
1810 easrc_priv = easrc->private;
1813 ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev);
1835 fsl_easrc_dump_firmware(easrc);
1843 struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id;
1844 struct device *dev = &easrc->pdev->dev;
1847 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
1864 { .compatible = "fsl,imx8mn-easrc",},
1873 struct fsl_asrc *easrc;
1880 easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL);
1881 if (!easrc)
1888 easrc->pdev = pdev;
1889 easrc->private = easrc_priv;
1899 easrc->paddr = res->start;
1901 easrc->regmap = devm_regmap_init_mmio_clk(dev, "mem", regs,
1903 if (IS_ERR(easrc->regmap)) {
1905 return PTR_ERR(easrc->regmap);
1915 dev_name(dev), easrc);
1921 easrc->mem_clk = devm_clk_get(dev, "mem");
1922 if (IS_ERR(easrc->mem_clk)) {
1924 return PTR_ERR(easrc->mem_clk);
1928 easrc->channel_avail = 32;
1929 easrc->get_dma_channel = fsl_easrc_get_dma_channel;
1930 easrc->request_pair = fsl_easrc_request_context;
1931 easrc->release_pair = fsl_easrc_release_context;
1932 easrc->get_fifo_addr = fsl_easrc_get_fifo_addr;
1933 easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv);
1938 ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate);
1945 easrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
1951 if (!(FSL_EASRC_FORMATS & (pcm_format_to_bits(easrc->asrc_format)))) {
1953 easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1963 platform_set_drvdata(pdev, easrc);
1966 spin_lock_init(&easrc->lock);
1968 regcache_cache_only(easrc->regmap, true);
2000 struct fsl_asrc *easrc = dev_get_drvdata(dev);
2001 struct fsl_easrc_priv *easrc_priv = easrc->private;
2004 regcache_cache_only(easrc->regmap, true);
2006 clk_disable_unprepare(easrc->mem_clk);
2008 spin_lock_irqsave(&easrc->lock, lock_flags);
2010 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2017 struct fsl_asrc *easrc = dev_get_drvdata(dev);
2018 struct fsl_easrc_priv *easrc_priv = easrc->private;
2025 ret = clk_prepare_enable(easrc->mem_clk);
2029 regcache_cache_only(easrc->regmap, false);
2030 regcache_mark_dirty(easrc->regmap);
2031 regcache_sync(easrc->regmap);
2033 spin_lock_irqsave(&easrc->lock, lock_flags);
2035 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2039 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2041 ret = fsl_easrc_get_firmware(easrc);
2052 ret = fsl_easrc_resampler_config(easrc);
2059 ctx = easrc->pair[i];
2072 ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
2079 ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
2091 clk_disable_unprepare(easrc->mem_clk);
2107 .name = "fsl-easrc",