Lines Matching refs:dev
39 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
45 i2s_write_reg(dev->i2s_base, TER(i), 0);
48 i2s_write_reg(dev->i2s_base, RER(i), 0);
52 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
58 i2s_read_reg(dev->i2s_base, TOR(i));
61 i2s_read_reg(dev->i2s_base, ROR(i));
65 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
72 irq = i2s_read_reg(dev->i2s_base, IMR(i));
73 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
77 irq = i2s_read_reg(dev->i2s_base, IMR(i));
78 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
83 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
90 irq = i2s_read_reg(dev->i2s_base, IMR(i));
91 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
95 irq = i2s_read_reg(dev->i2s_base, IMR(i));
96 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
103 struct dw_i2s_dev *dev = dev_id;
109 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
111 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
112 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
119 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
120 dw_pcm_push_tx(dev);
128 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
129 dw_pcm_pop_rx(dev);
135 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);
141 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);
152 static void i2s_start(struct dw_i2s_dev *dev,
155 struct i2s_clk_config_data *config = &dev->config;
157 i2s_write_reg(dev->i2s_base, IER, 1);
158 i2s_enable_irqs(dev, substream->stream, config->chan_nr);
161 i2s_write_reg(dev->i2s_base, ITER, 1);
163 i2s_write_reg(dev->i2s_base, IRER, 1);
165 i2s_write_reg(dev->i2s_base, CER, 1);
168 static void i2s_stop(struct dw_i2s_dev *dev,
172 i2s_clear_irqs(dev, substream->stream);
174 i2s_write_reg(dev->i2s_base, ITER, 0);
176 i2s_write_reg(dev->i2s_base, IRER, 0);
178 i2s_disable_irqs(dev, substream->stream, 8);
180 if (!dev->active) {
181 i2s_write_reg(dev->i2s_base, CER, 0);
182 i2s_write_reg(dev->i2s_base, IER, 0);
186 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
189 struct i2s_clk_config_data *config = &dev->config;
192 i2s_disable_channels(dev, stream);
196 i2s_write_reg(dev->i2s_base, TCR(ch_reg),
197 dev->xfer_resolution);
198 i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
199 dev->fifo_th - 1);
200 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
202 i2s_write_reg(dev->i2s_base, RCR(ch_reg),
203 dev->xfer_resolution);
204 i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
205 dev->fifo_th - 1);
206 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
215 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
216 struct i2s_clk_config_data *config = &dev->config;
222 dev->ccr = 0x00;
223 dev->xfer_resolution = 0x02;
228 dev->ccr = 0x08;
229 dev->xfer_resolution = 0x04;
234 dev->ccr = 0x10;
235 dev->xfer_resolution = 0x05;
239 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
252 dev_err(dev->dev, "channel not supported\n");
256 dw_i2s_config(dev, substream->stream);
258 i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
262 if (dev->capability & DW_I2S_MASTER) {
263 if (dev->i2s_clk_cfg) {
264 ret = dev->i2s_clk_cfg(config);
266 dev_err(dev->dev, "runtime audio clk config fail\n");
273 ret = clk_set_rate(dev->clk, bitclk);
275 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
287 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
290 i2s_write_reg(dev->i2s_base, TXFFR, 1);
292 i2s_write_reg(dev->i2s_base, RXFFR, 1);
300 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
307 dev->active++;
308 i2s_start(dev, substream);
314 dev->active--;
315 i2s_stop(dev, substream);
326 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
331 if (dev->capability & DW_I2S_SLAVE)
337 if (dev->capability & DW_I2S_MASTER)
347 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
362 static int dw_i2s_runtime_suspend(struct device *dev)
364 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
371 static int dw_i2s_runtime_resume(struct device *dev)
373 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
386 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
388 if (dev->capability & DW_I2S_MASTER)
389 clk_disable(dev->clk);
395 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
399 if (dev->capability & DW_I2S_MASTER) {
400 ret = clk_enable(dev->clk);
408 dw_i2s_config(dev, stream);
458 static int dw_configure_dai(struct dw_i2s_dev *dev,
466 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
467 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
471 if (dev->capability & DWC_I2S_RECORD &&
472 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
475 if (dev->capability & DWC_I2S_PLAY &&
476 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
480 dev_dbg(dev->dev, " designware: play supported\n");
484 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
494 dev_dbg(dev->dev, "designware: record supported\n");
498 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
508 dev_dbg(dev->dev, "designware: i2s master mode supported\n");
509 dev->capability |= DW_I2S_MASTER;
511 dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
512 dev->capability |= DW_I2S_SLAVE;
515 dev->fifo_th = fifo_depth / 2;
519 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
524 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
531 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
535 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
538 dev->play_dma_data.pd.data = pdata->play_dma_data;
539 dev->capture_dma_data.pd.data = pdata->capture_dma_data;
540 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
541 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
542 dev->play_dma_data.pd.max_burst = 16;
543 dev->capture_dma_data.pd.max_burst = 16;
544 dev->play_dma_data.pd.addr_width = bus_widths[idx];
545 dev->capture_dma_data.pd.addr_width = bus_widths[idx];
546 dev->play_dma_data.pd.filter = pdata->filter;
547 dev->capture_dma_data.pd.filter = pdata->filter;
552 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
556 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
557 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
566 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
573 dev->capability |= DWC_I2S_PLAY;
574 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
575 dev->play_dma_data.dt.addr_width = bus_widths[idx];
576 dev->play_dma_data.dt.fifo_size = fifo_depth *
578 dev->play_dma_data.dt.maxburst = 16;
583 dev->capability |= DWC_I2S_RECORD;
584 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
585 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
586 dev->capture_dma_data.dt.fifo_size = fifo_depth *
588 dev->capture_dma_data.dt.maxburst = 16;
597 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
599 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
605 const struct i2s_platform_data *pdata = pdev->dev.platform_data;
606 struct dw_i2s_dev *dev;
612 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
613 if (!dev)
616 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
624 dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
625 if (IS_ERR(dev->i2s_base))
626 return PTR_ERR(dev->i2s_base);
628 dev->dev = &pdev->dev;
632 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
633 pdev->name, dev);
635 dev_err(&pdev->dev, "failed to request irq\n");
640 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
641 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
643 dev->capability = pdata->cap;
645 dev->quirks = pdata->quirks;
646 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
647 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
648 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
650 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
653 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
658 if (dev->capability & DW_I2S_MASTER) {
660 dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
661 if (!dev->i2s_clk_cfg) {
662 dev_err(&pdev->dev, "no clock configure method\n");
666 dev->clk = devm_clk_get(&pdev->dev, clk_id);
668 if (IS_ERR(dev->clk))
669 return PTR_ERR(dev->clk);
671 ret = clk_prepare_enable(dev->clk);
676 dev_set_drvdata(&pdev->dev, dev);
677 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
680 dev_err(&pdev->dev, "not able to register dai\n");
687 dev->use_pio = true;
689 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
691 dev->use_pio = false;
695 dev_err(&pdev->dev, "could not register pcm: %d\n",
701 pm_runtime_enable(&pdev->dev);
705 if (dev->capability & DW_I2S_MASTER)
706 clk_disable_unprepare(dev->clk);
712 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
714 if (dev->capability & DW_I2S_MASTER)
715 clk_disable_unprepare(dev->clk);
717 pm_runtime_disable(&pdev->dev);