Lines Matching refs:base
852 return mem->base + (offset * 3);
857 return mem->base + (offset * 2);
870 return mem->base + (offset * 4);
873 return (mem->base + (offset * 3)) & ~0x3;
875 return mem->base + (offset * 5);
889 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]);
945 adsp_err(dsp, "No base for region %x\n",
950 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset);
2119 ctl->alg_region.base = alg_region->base;
2191 __be32 base)
2201 alg_region->base = be32_to_cpu(base);
2251 int *type, __be32 *base)
2257 alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]);
2279 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2380 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2520 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id,
2683 adsp_err(dsp, "No base for region %x\n", type);
2690 reg = alg_region->base;
2828 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2846 dsp->base + ADSP1_CONTROL_31,
2880 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2892 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2895 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2898 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2917 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2933 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2957 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2974 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
2997 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3003 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3009 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
3010 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
3011 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
3013 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3019 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
3020 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
3021 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
3084 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 },
3085 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA },
3086 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF },
3087 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF },
3088 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions },
3089 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions },
3090 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions },
3091 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF },
3092 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF },
3093 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions },
3094 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions },
3095 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions },
3096 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF },
3097 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF },
3098 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions },
3099 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions },
3100 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions },
3101 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF },
3102 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF },
3103 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions },
3104 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions },
3105 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions },
3106 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 },
3119 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING,
3174 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
3180 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL,
3228 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3235 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3343 dsp->base + HALO_CCM_CORE_CONTROL,
3349 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
3353 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET,
3394 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3776 "region=%d type=%d base=%08x off=%08x size=%08x\n",
3831 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3839 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
4381 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
4400 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
4412 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
4428 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
4444 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 },
4445 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 },
4446 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 },
4473 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR,