Lines Matching defs:component
338 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
341 reg = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
359 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
360 unsigned int reg_pwr = snd_soc_component_read(component, WM9081_POWER_MANAGEMENT);
361 unsigned int reg2 = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
382 snd_soc_component_write(component, WM9081_ANALOGUE_SPEAKER_2, reg2);
545 static int wm9081_set_fll(struct snd_soc_component *component, int fll_id,
548 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
560 dev_dbg(component->dev, "FLL disabled\n");
571 reg5 = snd_soc_component_read(component, WM9081_FLL_CONTROL_5);
580 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
585 clk_sys_reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
587 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3,
592 reg1 = snd_soc_component_read(component, WM9081_FLL_CONTROL_1);
594 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
601 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
603 snd_soc_component_write(component, WM9081_FLL_CONTROL_2,
606 snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k);
608 reg4 = snd_soc_component_read(component, WM9081_FLL_CONTROL_4);
611 snd_soc_component_write(component, WM9081_FLL_CONTROL_4, reg4);
615 snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5);
618 snd_soc_component_update_bits(component, WM9081_FLL_CONTROL_4,
622 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
626 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
628 dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
636 static int configure_clock(struct snd_soc_component *component)
638 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
653 wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK, 0, 0);
694 ret = wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK,
710 reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_1);
715 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_1, reg);
717 reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
722 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, reg);
724 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
732 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
733 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
738 dev_dbg(component->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
741 dev_dbg(component->dev, "Using %dHz MCLK with FLL\n",
745 dev_err(component->dev, "System clock not configured\n");
751 configure_clock(component);
756 wm9081_set_fll(component, 0, 0, 0);
815 static int wm9081_set_bias_level(struct snd_soc_component *component,
818 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
826 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
830 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
836 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
841 snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
845 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
850 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
858 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
862 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
867 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
871 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
878 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
883 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
888 snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
902 struct snd_soc_component *component = dai->component;
903 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
904 unsigned int aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
986 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
995 struct snd_soc_component *component = dai->component;
996 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1000 clk_ctrl2 = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_2);
1003 aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
1005 aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
1008 aif3 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_3);
1011 aif4 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_4);
1047 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1049 ret = configure_clock(component);
1065 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1081 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1100 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1105 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1126 dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
1130 eq1 = snd_soc_component_read(component, WM9081_EQ_1) & WM9081_EQ_ENA;
1132 snd_soc_component_write(component, WM9081_EQ_1, 0);
1136 snd_soc_component_write(component, WM9081_EQ_1 + i, s->config[i]);
1139 snd_soc_component_write(component, WM9081_EQ_1, eq1);
1142 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1143 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
1144 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_3, aif3);
1145 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_4, aif4);
1152 struct snd_soc_component *component = codec_dai->component;
1155 reg = snd_soc_component_read(component, WM9081_DAC_DIGITAL_2);
1162 snd_soc_component_write(component, WM9081_DAC_DIGITAL_2, reg);
1167 static int wm9081_set_sysclk(struct snd_soc_component *component, int clk_id,
1170 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1189 struct snd_soc_component *component = dai->component;
1190 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1191 unsigned int aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
1221 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_1, aif1);
1255 static int wm9081_probe(struct snd_soc_component *component)
1257 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1260 snd_soc_component_update_bits(component, WM9081_ANALOGUE_LINEOUT,
1262 snd_soc_component_update_bits(component, WM9081_ANALOGUE_SPEAKER_PGA,
1266 dev_dbg(component->dev,
1268 snd_soc_add_component_controls(component, wm9081_eq_controls,