Lines Matching refs:x0001
777 #define WM8996_BG_ENA 0x0001 /* BG_ENA */
778 #define WM8996_BG_ENA_MASK 0x0001 /* BG_ENA */
841 #define WM8996_ADCR_ENA 0x0001 /* ADCR_ENA */
842 #define WM8996_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
877 #define WM8996_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */
878 #define WM8996_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */
913 #define WM8996_DAC1R_ENA 0x0001 /* DAC1R_ENA */
914 #define WM8996_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
949 #define WM8996_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */
950 #define WM8996_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */
998 #define WM8996_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */
999 #define WM8996_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */
1197 #define WM8996_MICB1_DISCH 0x0001 /* MICB1_DISCH */
1198 #define WM8996_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
1216 #define WM8996_MICB2_DISCH 0x0001 /* MICB2_DISCH */
1217 #define WM8996_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
1231 #define WM8996_LDO1_DISCH 0x0001 /* LDO1_DISCH */
1232 #define WM8996_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
1246 #define WM8996_LDO2_DISCH 0x0001 /* LDO2_DISCH */
1247 #define WM8996_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
1269 #define WM8996_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */
1270 #define WM8996_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */
1287 #define WM8996_HP_POLL 0x0001 /* HP_POLL */
1288 #define WM8996_HP_POLL_MASK 0x0001 /* HP_POLL */
1316 #define WM8996_MICD_ENA 0x0001 /* MICD_ENA */
1317 #define WM8996_MICD_ENA_MASK 0x0001 /* MICD_ENA */
1338 #define WM8996_MICD_STS 0x0001 /* MICD_STS */
1339 #define WM8996_MICD_STS_MASK 0x0001 /* MICD_STS */
1374 #define WM8996_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
1375 #define WM8996_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
1442 #define WM8996_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
1443 #define WM8996_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
1619 #define WM8996_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */
1620 #define WM8996_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */
1670 #define WM8996_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */
1671 #define WM8996_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */
1682 #define WM8996_FLL_ENA 0x0001 /* FLL_ENA */
1683 #define WM8996_FLL_ENA_MASK 0x0001 /* FLL_ENA */
1741 #define WM8996_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */
1742 #define WM8996_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */
1759 #define WM8996_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */
1760 #define WM8996_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */
1816 #define WM8996_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
1817 #define WM8996_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
1839 #define WM8996_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
1840 #define WM8996_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
1857 #define WM8996_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */
1858 #define WM8996_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */
2087 #define WM8996_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */
2088 #define WM8996_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */
2103 #define WM8996_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */
2104 #define WM8996_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */
2160 #define WM8996_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
2161 #define WM8996_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
2183 #define WM8996_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
2184 #define WM8996_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
2201 #define WM8996_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */
2202 #define WM8996_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */
2287 #define WM8996_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */
2288 #define WM8996_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */
2295 #define WM8996_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */
2296 #define WM8996_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */
2438 #define WM8996_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */
2439 #define WM8996_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */
2513 #define WM8996_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */
2514 #define WM8996_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */
2792 #define WM8996_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */
2793 #define WM8996_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */
2867 #define WM8996_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */
2868 #define WM8996_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */
3033 #define WM8996_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */
3034 #define WM8996_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */
3053 #define WM8996_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */
3054 #define WM8996_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */
3083 #define WM8996_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */
3084 #define WM8996_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */
3103 #define WM8996_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */
3104 #define WM8996_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */
3115 #define WM8996_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */
3116 #define WM8996_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */
3127 #define WM8996_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */
3128 #define WM8996_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */
3139 #define WM8996_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */
3140 #define WM8996_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */
3151 #define WM8996_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */
3152 #define WM8996_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */
3159 #define WM8996_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */
3160 #define WM8996_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */
3171 #define WM8996_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
3172 #define WM8996_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
3191 #define WM8996_DAC_OSR128 0x0001 /* DAC_OSR128 */
3192 #define WM8996_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
3214 #define WM8996_STL_SEL 0x0001 /* STL_SEL */
3215 #define WM8996_STL_SEL_MASK 0x0001 /* STL_SEL */
3441 #define WM8996_BCLK1_PD 0x0001 /* BCLK1_PD */
3442 #define WM8996_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
3477 #define WM8996_BCLK2_PD 0x0001 /* BCLK2_PD */
3478 #define WM8996_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */
3501 #define WM8996_GP1_EINT 0x0001 /* GP1_EINT */
3502 #define WM8996_GP1_EINT_MASK 0x0001 /* GP1_EINT */
3545 #define WM8996_MICD_EINT 0x0001 /* MICD_EINT */
3546 #define WM8996_MICD_EINT_MASK 0x0001 /* MICD_EINT */
3601 #define WM8996_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
3602 #define WM8996_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
3645 #define WM8996_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */
3646 #define WM8996_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */
3653 #define WM8996_IM_IRQ 0x0001 /* IM_IRQ */
3654 #define WM8996_IM_IRQ_MASK 0x0001 /* IM_IRQ */