Lines Matching refs:freq_in
2123 int freq_in, int freq_out)
2128 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2132 while (freq_in > 13500000) {
2134 freq_in /= 2;
2139 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2151 if (freq_in > 1000000) {
2153 } else if (freq_in > 256000) {
2155 freq_in *= 2;
2156 } else if (freq_in > 128000) {
2158 freq_in *= 4;
2159 } else if (freq_in > 64000) {
2161 freq_in *= 8;
2164 freq_in *= 16;
2166 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2169 Ndiv = freq_out / freq_in;
2172 Nmod = freq_out % freq_in;
2180 do_div(Kpart, freq_in);
2195 gcd_fll = gcd(freq_out, freq_in);
2197 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2198 fll->lambda = freq_in / gcd_fll;
2206 unsigned int freq_in, unsigned int freq_out)
2248 freq_in = 12000000;
2257 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2265 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2313 freq_in == freq_out && freq_out) {
2433 wm8994->fll[id].in = freq_in;
2482 unsigned int freq_in, unsigned int freq_out)
2484 return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);