Lines Matching refs:x0001
175 #define WM8993_BIAS_ENA 0x0001 /* BIAS_ENA */
176 #define WM8993_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
223 #define WM8993_ADCR_ENA 0x0001 /* ADCR_ENA */
224 #define WM8993_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
275 #define WM8993_DACR_ENA 0x0001 /* DACR_ENA */
276 #define WM8993_DACR_ENA_MASK 0x0001 /* DACR_ENA */
356 #define WM8993_LOOPBACK 0x0001 /* LOOPBACK */
357 #define WM8993_LOOPBACK_MASK 0x0001 /* LOOPBACK */
465 #define WM8993_DACR_DATINV 0x0001 /* DACR_DATINV */
466 #define WM8993_DACR_DATINV_MASK 0x0001 /* DACR_DATINV */
526 #define WM8993_ADCR_DATINV 0x0001 /* ADCR_DATINV */
527 #define WM8993_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
596 #define WM8993_GPIO1_EINT 0x0001 /* GPIO1_EINT */
597 #define WM8993_GPIO1_EINT_MASK 0x0001 /* GPIO1_EINT */
655 #define WM8993_GPIO1_DB 0x0001 /* GPIO1_DB */
656 #define WM8993_GPIO1_DB_MASK 0x0001 /* GPIO1_DB */
715 #define WM8993_GPI7_ENA 0x0001 /* GPI7_ENA */
716 #define WM8993_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */
763 #define WM8993_GPIO1_POL 0x0001 /* GPIO1_POL */
764 #define WM8993_GPIO1_POL_MASK 0x0001 /* GPIO1_POL */
905 #define WM8993_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */
906 #define WM8993_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */
1033 #define WM8993_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */
1034 #define WM8993_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */
1117 #define WM8993_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */
1118 #define WM8993_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */
1223 #define WM8993_DACL_TO_MIXOUTL 0x0001 /* DACL_TO_MIXOUTL */
1224 #define WM8993_DACL_TO_MIXOUTL_MASK 0x0001 /* DACL_TO_MIXOUTL */
1263 #define WM8993_DACR_TO_MIXOUTR 0x0001 /* DACR_TO_MIXOUTR */
1264 #define WM8993_DACR_TO_MIXOUTR_MASK 0x0001 /* DACR_TO_MIXOUTR */
1371 #define WM8993_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */
1372 #define WM8993_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */
1399 #define WM8993_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */
1400 #define WM8993_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */
1439 #define WM8993_DACR_TO_SPKMIXR 0x0001 /* DACR_TO_SPKMIXR */
1440 #define WM8993_DACR_TO_SPKMIXR_MASK 0x0001 /* DACR_TO_SPKMIXR */
1455 #define WM8993_VROI 0x0001 /* VROI */
1456 #define WM8993_VROI_MASK 0x0001 /* VROI */
1498 #define WM8993_VMID_DISCH 0x0001 /* VMID_DISCH */
1499 #define WM8993_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */
1520 #define WM8993_MICB1_LVL 0x0001 /* MICB1_LVL */
1521 #define WM8993_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */
1536 #define WM8993_FLL_ENA 0x0001 /* FLL_ENA */
1537 #define WM8993_FLL_ENA_MASK 0x0001 /* FLL_ENA */
1600 #define WM8993_CLK_DSP_ENA 0x0001 /* CLK_DSP_ENA */
1601 #define WM8993_CLK_DSP_ENA_MASK 0x0001 /* CLK_DSP_ENA */
1615 #define WM8993_SR_MODE 0x0001 /* SR_MODE */
1616 #define WM8993_SR_MODE_MASK 0x0001 /* SR_MODE */
1623 #define WM8993_MASK_WRITE_ENA 0x0001 /* MASK_WRITE_ENA */
1624 #define WM8993_MASK_WRITE_ENA_MASK 0x0001 /* MASK_WRITE_ENA */
1692 #define WM8993_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
1693 #define WM8993_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
1719 #define WM8993_CP_DYN_V 0x0001 /* CP_DYN_V */
1720 #define WM8993_CP_DYN_V_MASK 0x0001 /* CP_DYN_V */
1763 #define WM8993_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
1764 #define WM8993_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
1857 #define WM8993_EQ_ENA 0x0001 /* EQ_ENA */
1858 #define WM8993_EQ_ENA_MASK 0x0001 /* EQ_ENA */
2054 #define WM8993_BCLK_PD 0x0001 /* BCLK_PD */
2055 #define WM8993_BCLK_PD_MASK 0x0001 /* BCLK_PD */