Lines Matching refs:f_mclk
99 unsigned int f_mclk;
445 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
450 static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
458 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
475 unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
479 if (!f_mclk)
490 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
493 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
494 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
496 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
499 if (4 * f_opclk < 3 * f_mclk)
501 opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
515 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
518 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
519 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
522 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
534 wm8978->f_mclk, wm8978->f_pllout);
536 pll_factors(component, &pll_div, f2, wm8978->f_mclk);
573 if (wm8978->f_mclk)
617 wm8978->f_mclk = freq;
732 if (!wm8978->f_mclk)
777 f_sel = wm8978->f_mclk;