Lines Matching defs:component
339 struct snd_soc_component *component = codec_dai->component;
340 u16 iface = snd_soc_component_read(component, WM8940_IFACE) & 0xFE67;
341 u16 clk = snd_soc_component_read(component, WM8940_CLOCK) & 0x1fe;
352 snd_soc_component_write(component, WM8940_CLOCK, clk);
385 snd_soc_component_write(component, WM8940_IFACE, iface);
394 struct snd_soc_component *component = dai->component;
395 u16 iface = snd_soc_component_read(component, WM8940_IFACE) & 0xFD9F;
396 u16 addcntrl = snd_soc_component_read(component, WM8940_ADDCNTRL) & 0xFFF1;
397 u16 companding = snd_soc_component_read(component,
426 ret = snd_soc_component_write(component, WM8940_ADDCNTRL, addcntrl);
446 ret = snd_soc_component_write(component, WM8940_COMPANDINGCTL, companding);
449 ret = snd_soc_component_write(component, WM8940_IFACE, iface);
457 struct snd_soc_component *component = dai->component;
458 u16 mute_reg = snd_soc_component_read(component, WM8940_DAC) & 0xffbf;
463 return snd_soc_component_write(component, WM8940_DAC, mute_reg);
466 static int wm8940_set_bias_level(struct snd_soc_component *component,
469 struct wm8940_priv *wm8940 = snd_soc_component_get_drvdata(component);
471 u16 pwr_reg = snd_soc_component_read(component, WM8940_POWER1) & 0x1F0;
479 val = snd_soc_component_read(component, WM8940_OUTPUTCTL);
480 ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, val | 0x2);
484 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1);
489 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1);
492 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
495 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
503 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x2);
506 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg);
576 struct snd_soc_component *component = codec_dai->component;
580 reg = snd_soc_component_read(component, WM8940_POWER1);
581 snd_soc_component_write(component, WM8940_POWER1, reg & 0x1df);
585 reg = snd_soc_component_read(component, WM8940_CLOCK);
586 snd_soc_component_write(component, WM8940_CLOCK, reg & 0x0ff);
588 snd_soc_component_write(component, WM8940_PLLN, (1 << 7));
595 snd_soc_component_write(component, WM8940_PLLN,
597 else /* No factional component */
598 snd_soc_component_write(component, WM8940_PLLN,
600 snd_soc_component_write(component, WM8940_PLLK1, pll_div.k >> 18);
601 snd_soc_component_write(component, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
602 snd_soc_component_write(component, WM8940_PLLK3, pll_div.k & 0x1ff);
604 reg = snd_soc_component_read(component, WM8940_POWER1);
605 snd_soc_component_write(component, WM8940_POWER1, reg | 0x020);
608 reg = snd_soc_component_read(component, WM8940_CLOCK);
609 snd_soc_component_write(component, WM8940_CLOCK, reg | 0x100);
617 struct snd_soc_component *component = codec_dai->component;
618 struct wm8940_priv *wm8940 = snd_soc_component_get_drvdata(component);
635 struct snd_soc_component *component = codec_dai->component;
641 reg = snd_soc_component_read(component, WM8940_CLOCK) & 0xFFE3;
642 ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 2));
645 reg = snd_soc_component_read(component, WM8940_CLOCK) & 0xFF1F;
646 ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 5));
649 reg = snd_soc_component_read(component, WM8940_GPIO) & 0xFFCF;
650 ret = snd_soc_component_write(component, WM8940_GPIO, reg | (div << 4));
694 static int wm8940_probe(struct snd_soc_component *component)
696 struct wm8940_setup_data *pdata = component->dev->platform_data;
700 ret = wm8940_reset(component);
702 dev_err(component->dev, "Failed to issue reset\n");
706 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
708 ret = snd_soc_component_write(component, WM8940_POWER1, 0x180);
713 dev_warn(component->dev, "No platform data supplied\n");
715 reg = snd_soc_component_read(component, WM8940_OUTPUTCTL);
716 ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, reg | pdata->vroi);