Lines Matching refs:x0001
164 #define WM8904_BIAS_ENA 0x0001 /* BIAS_ENA */
165 #define WM8904_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
179 #define WM8904_VMID_ENA 0x0001 /* VMID_ENA */
180 #define WM8904_VMID_ENA_MASK 0x0001 /* VMID_ENA */
213 #define WM8904_ADC_OSR128 0x0001 /* ADC_OSR128 */
214 #define WM8904_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */
225 #define WM8904_INR_ENA 0x0001 /* INR_ENA */
226 #define WM8904_INR_ENA_MASK 0x0001 /* INR_ENA */
237 #define WM8904_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */
238 #define WM8904_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */
249 #define WM8904_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */
250 #define WM8904_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */
269 #define WM8904_ADCR_ENA 0x0001 /* ADCR_ENA */
270 #define WM8904_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
289 #define WM8904_MCLK_DIV 0x0001 /* MCLK_DIV */
290 #define WM8904_MCLK_DIV_MASK 0x0001 /* MCLK_DIV */
331 #define WM8904_TOCLK_ENA 0x0001 /* TOCLK_ENA */
332 #define WM8904_TOCLK_ENA_MASK 0x0001 /* TOCLK_ENA */
382 #define WM8904_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
383 #define WM8904_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
555 #define WM8904_ADCR_DATINV 0x0001 /* ADCR_DATINV */
556 #define WM8904_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
605 #define WM8904_DRC_GS_HYST 0x0001 /* DRC_GS_HYST */
606 #define WM8904_DRC_GS_HYST_MASK 0x0001 /* DRC_GS_HYST */
799 #define WM8904_LINEOUTR_BYP_ENA 0x0001 /* LINEOUTR_BYP_ENA */
800 #define WM8904_LINEOUTR_BYP_ENA_MASK 0x0001 /* LINEOUTR_BYP_ENA */
819 #define WM8904_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
820 #define WM8904_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
887 #define WM8904_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
888 #define WM8904_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
988 #define WM8904_HPR_ENA 0x0001 /* HPR_ENA */
989 #define WM8904_HPR_ENA_MASK 0x0001 /* HPR_ENA */
1024 #define WM8904_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */
1025 #define WM8904_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */
1032 #define WM8904_CP_ENA 0x0001 /* CP_ENA */
1033 #define WM8904_CP_ENA_MASK 0x0001 /* CP_ENA */
1040 #define WM8904_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
1041 #define WM8904_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
1104 #define WM8904_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
1105 #define WM8904_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
1120 #define WM8904_FLL_ENA 0x0001 /* FLL_ENA */
1121 #define WM8904_FLL_ENA_MASK 0x0001 /* FLL_ENA */
1196 #define WM8904_BCLK_PD 0x0001 /* BCLK_PD */
1197 #define WM8904_BCLK_PD_MASK 0x0001 /* BCLK_PD */
1244 #define WM8904_MIC_DET_EINT 0x0001 /* MIC_DET_EINT */
1245 #define WM8904_MIC_DET_EINT_MASK 0x0001 /* MIC_DET_EINT */
1288 #define WM8904_IM_MIC_DET_EINT 0x0001 /* IM_MIC_DET_EINT */
1289 #define WM8904_IM_MIC_DET_EINT_MASK 0x0001 /* IM_MIC_DET_EINT */
1332 #define WM8904_MIC_DET_EINT_POL 0x0001 /* MIC_DET_EINT_POL */
1333 #define WM8904_MIC_DET_EINT_POL_MASK 0x0001 /* MIC_DET_EINT_POL */
1376 #define WM8904_MIC_DET_EINT_DB 0x0001 /* MIC_DET_EINT_DB */
1377 #define WM8904_MIC_DET_EINT_DB_MASK 0x0001 /* MIC_DET_EINT_DB */
1384 #define WM8904_EQ_ENA 0x0001 /* EQ_ENA */
1385 #define WM8904_EQ_ENA_MASK 0x0001 /* EQ_ENA */
1564 #define WM8904_ADC_BIASX1P5 0x0001 /* ADC_BIASX1P5 */
1578 #define WM8904_FLL_FRC_NCO 0x0001 /* FLL_FRC_NCO */
1579 #define WM8904_FLL_FRC_NCO_MASK 0x0001 /* FLL_FRC_NCO */