Lines Matching refs:x0001
139 #define WM8903_BIAS_ENA 0x0001 /* BIAS_ENA */
140 #define WM8903_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
165 #define WM8903_VMID_BUF_ENA 0x0001 /* VMID_BUF_ENA */
166 #define WM8903_VMID_BUF_ENA_MASK 0x0001 /* VMID_BUF_ENA */
187 #define WM8903_ADC_OSR128 0x0001 /* ADC_OSR128 */
188 #define WM8903_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */
199 #define WM8903_INR_ENA 0x0001 /* INR_ENA */
200 #define WM8903_INR_ENA_MASK 0x0001 /* INR_ENA */
211 #define WM8903_MIXOUTR_ENA 0x0001 /* MIXOUTR_ENA */
212 #define WM8903_MIXOUTR_ENA_MASK 0x0001 /* MIXOUTR_ENA */
223 #define WM8903_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */
224 #define WM8903_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */
235 #define WM8903_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */
236 #define WM8903_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */
247 #define WM8903_MIXSPKR_ENA 0x0001 /* MIXSPKR_ENA */
248 #define WM8903_MIXSPKR_ENA_MASK 0x0001 /* MIXSPKR_ENA */
259 #define WM8903_SPKR_ENA 0x0001 /* SPKR_ENA */
260 #define WM8903_SPKR_ENA_MASK 0x0001 /* SPKR_ENA */
279 #define WM8903_ADCR_ENA 0x0001 /* ADCR_ENA */
280 #define WM8903_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
287 #define WM8903_MCLKDIV2 0x0001 /* MCLKDIV2 */
288 #define WM8903_MCLKDIV2_MASK 0x0001 /* MCLKDIV2 */
316 #define WM8903_TO_ENA 0x0001 /* TO_ENA */
317 #define WM8903_TO_ENA_MASK 0x0001 /* TO_ENA */
367 #define WM8903_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
368 #define WM8903_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
529 #define WM8903_ADCR_DATINV 0x0001 /* ADCR_DATINV */
530 #define WM8903_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
583 #define WM8903_DRC_HYST_ENA 0x0001 /* DRC_HYST_ENA */
584 #define WM8903_DRC_HYST_ENA_MASK 0x0001 /* DRC_HYST_ENA */
701 #define WM8903_BYPASSR_TO_MIXOUTL 0x0001 /* BYPASSR_TO_MIXOUTL */
702 #define WM8903_BYPASSR_TO_MIXOUTL_MASK 0x0001 /* BYPASSR_TO_MIXOUTL */
721 #define WM8903_BYPASSR_TO_MIXOUTR 0x0001 /* BYPASSR_TO_MIXOUTR */
722 #define WM8903_BYPASSR_TO_MIXOUTR_MASK 0x0001 /* BYPASSR_TO_MIXOUTR */
741 #define WM8903_BYPASSR_TO_MIXSPKL 0x0001 /* BYPASSR_TO_MIXSPKL */
742 #define WM8903_BYPASSR_TO_MIXSPKL_MASK 0x0001 /* BYPASSR_TO_MIXSPKL */
761 #define WM8903_BYPASSR_MIXSPKL_VOL 0x0001 /* BYPASSR_MIXSPKL_VOL */
762 #define WM8903_BYPASSR_MIXSPKL_VOL_MASK 0x0001 /* BYPASSR_MIXSPKL_VOL */
781 #define WM8903_BYPASSR_TO_MIXSPKR 0x0001 /* BYPASSR_TO_MIXSPKR */
782 #define WM8903_BYPASSR_TO_MIXSPKR_MASK 0x0001 /* BYPASSR_TO_MIXSPKR */
801 #define WM8903_BYPASSR_MIXSPKR_VOL 0x0001 /* BYPASSR_MIXSPKR_VOL */
802 #define WM8903_BYPASSR_MIXSPKR_VOL_MASK 0x0001 /* BYPASSR_MIXSPKR_VOL */
927 #define WM8903_VROI 0x0001 /* VROI */
928 #define WM8903_VROI_MASK 0x0001 /* VROI */
981 #define WM8903_HPR_ENA 0x0001 /* HPR_ENA */
982 #define WM8903_HPR_ENA_MASK 0x0001 /* HPR_ENA */
1017 #define WM8903_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */
1018 #define WM8903_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */
1025 #define WM8903_CP_ENA 0x0001 /* CP_ENA */
1026 #define WM8903_CP_ENA_MASK 0x0001 /* CP_ENA */
1037 #define WM8903_CP_DYN_V 0x0001 /* CP_DYN_V */
1038 #define WM8903_CP_DYN_V_MASK 0x0001 /* CP_DYN_V */
1101 #define WM8903_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
1102 #define WM8903_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
1109 #define WM8903_MASK_WRITE_ENA 0x0001 /* MASK_WRITE_ENA */
1110 #define WM8903_MASK_WRITE_ENA_MASK 0x0001 /* MASK_WRITE_ENA */
1145 #define WM8903_GP1_EINT 0x0001 /* GP1_EINT */
1146 #define WM8903_GP1_EINT_MASK 0x0001 /* GP1_EINT */
1181 #define WM8903_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
1182 #define WM8903_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
1201 #define WM8903_IRQ_POL 0x0001 /* IRQ_POL */
1202 #define WM8903_IRQ_POL_MASK 0x0001 /* IRQ_POL */