Lines Matching refs:x2000
1083 #define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */
1084 #define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */
1108 #define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */
1109 #define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */
1140 #define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */
1141 #define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */
1165 #define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */
1166 #define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */
1402 #define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */
1403 #define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */
1563 #define WM5100_IN1_OSR 0x2000 /* IN1_OSR */
1564 #define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */
1587 #define WM5100_IN2_OSR 0x2000 /* IN2_OSR */
1588 #define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */
1611 #define WM5100_IN3_OSR 0x2000 /* IN3_OSR */
1612 #define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */
1635 #define WM5100_IN4_OSR 0x2000 /* IN4_OSR */
1636 #define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */
1911 #define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */
1912 #define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
1955 #define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */
1956 #define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
1999 #define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */
2000 #define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */
2043 #define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */
2044 #define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */
2069 #define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */
2070 #define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */
2095 #define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */
2096 #define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */
2326 #define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
2327 #define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
2353 #define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */
2354 #define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */
3013 #define WM5100_GP1_PD 0x2000 /* GP1_PD */
3014 #define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */
3048 #define WM5100_GP2_PD 0x2000 /* GP2_PD */
3049 #define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */
3083 #define WM5100_GP3_PD 0x2000 /* GP3_PD */
3084 #define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */
3118 #define WM5100_GP4_PD 0x2000 /* GP4_PD */
3119 #define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */
3153 #define WM5100_GP5_PD 0x2000 /* GP5_PD */
3154 #define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */
3188 #define WM5100_GP6_PD 0x2000 /* GP6_PD */
3189 #define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */
3219 #define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */
3220 #define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
3414 #define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */
3415 #define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */
3454 #define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */
3455 #define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */
3550 #define WM5100_HPDET_STS 0x2000 /* HPDET_STS */
3551 #define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */
3586 #define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */
3587 #define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */
3710 #define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */
3711 #define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */
3750 #define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */
3751 #define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */