Lines Matching defs:component
87 struct snd_soc_component *component;
1553 static int wm2200_probe(struct snd_soc_component *component)
1555 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1557 wm2200->component = component;
1564 struct snd_soc_component *component = dai->component;
1578 dev_err(component->dev, "Unsupported DAI format %d\n",
1597 dev_err(component->dev, "Unsupported master mode %d\n",
1619 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_1, WM2200_AIF1_BCLK_MSTR |
1621 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_2,
1624 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_3,
1627 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_5,
1696 struct snd_soc_component *component = dai->component;
1697 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1709 dev_dbg(component->dev, "Word length %d bits, frame length %d bits\n",
1718 dev_err(component->dev, "SYSCLK has no rate set\n");
1726 dev_err(component->dev, "Unsupported sample rate: %dHz\n",
1732 dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz SYSCLK\n",
1744 dev_err(component->dev,
1751 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1752 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_1,
1756 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1759 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_7,
1762 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_6,
1767 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_9,
1771 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_8,
1775 snd_soc_component_update_bits(component, WM2200_CLOCKING_4,
1786 static int wm2200_set_sysclk(struct snd_soc_component *component, int clk_id,
1789 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1797 dev_err(component->dev, "Unknown clock %d\n", clk_id);
1808 dev_err(component->dev, "Invalid source %d\n", source);
1818 dev_err(component->dev, "Invalid clock rate: %d\n", freq);
1826 snd_soc_component_update_bits(component, WM2200_CLOCKING_3, WM2200_SYSCLK_FREQ_MASK |
1934 static int wm2200_set_fll(struct snd_soc_component *component, int fll_id, int source,
1937 struct i2c_client *i2c = to_i2c_client(component->dev);
1938 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
1944 dev_dbg(component->dev, "FLL disabled");
1947 pm_runtime_put(component->dev);
1950 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1,
1961 dev_err(component->dev, "Invalid FLL source %d\n", source);
1970 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1, WM2200_FLL_ENA, 0);
1972 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_2,
1977 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_3,
1980 snd_soc_component_update_bits(component, WM2200_FLL_EFS_2,
1984 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_3,
1986 snd_soc_component_update_bits(component, WM2200_FLL_EFS_2,
1990 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_4, WM2200_FLL_THETA_MASK,
1992 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_6, WM2200_FLL_N_MASK,
1994 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_7,
1999 snd_soc_component_update_bits(component, WM2200_FLL_EFS_1,
2005 pm_runtime_get_sync(component->dev);
2007 snd_soc_component_update_bits(component, WM2200_FLL_CONTROL_1,
2015 snd_soc_component_update_bits(component, WM2200_CLOCKING_3, WM2200_SYSCLK_ENA,
2030 ret = snd_soc_component_read(component,
2033 dev_err(component->dev,
2042 dev_err(component->dev, "FLL lock timed out\n");
2043 pm_runtime_put(component->dev);
2051 dev_dbg(component->dev, "FLL running %dHz->%dHz\n", Fref, Fout);
2058 struct snd_soc_component *component = dai->component;
2059 struct wm2200_priv *wm2200 = snd_soc_component_get_drvdata(component);
2063 ret = snd_soc_component_read(component, WM2200_GPIO_CTRL_1);
2070 dev_err(component->dev, "Failed to read GPIO 1 config: %d\n", ret);
2073 snd_soc_component_update_bits(component, WM2200_AUDIO_IF_1_2,