Lines Matching defs:bclk
1565 int lrclk, bclk, fmt_val;
1568 bclk = 0;
1590 bclk |= WM2200_AIF1_BCLK_MSTR;
1594 bclk |= WM2200_AIF1_BCLK_MSTR;
1606 bclk |= WM2200_AIF1_BCLK_INV;
1610 bclk |= WM2200_AIF1_BCLK_INV;
1620 WM2200_AIF1_BCLK_INV, bclk);
1698 int i, bclk, lrclk, wl, fl, sr_code;
1713 bclk = snd_soc_params_to_bclk(params);
1714 if (bclk < 0)
1715 return bclk;
1733 bclk, wm2200->sysclk);
1741 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1746 bclk, wm2200->sysclk);
1750 bclk = i;
1751 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1753 WM2200_AIF1_BCLK_DIV_MASK, bclk);
1755 lrclk = bclk_rates[bclk] / params_rate(params);
1756 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);