Lines Matching defs:IIR1
144 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
154 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
164 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
397 IIR1,
589 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
2816 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
2818 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
2820 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
2822 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
3260 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
3263 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
3266 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
3269 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
3301 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3303 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3305 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3307 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3309 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3327 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
3328 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
3329 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
3330 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
3331 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
4549 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
4550 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
4551 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
4552 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
4557 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
4999 {"SRC1", NULL, "IIR1"},