Lines Matching refs:dac33
163 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
164 u8 *cache = dac33->reg_cache;
174 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
175 u8 *cache = dac33->reg_cache;
185 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
191 if (dac33->chip_power) {
192 val = i2c_smbus_read_byte_data(dac33->i2c, value[0]);
211 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
217 * D15..D8 dac33 register offset
224 if (dac33->chip_power) {
225 ret = i2c_master_send(dac33->i2c, data, 2);
238 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
241 mutex_lock(&dac33->mutex);
243 mutex_unlock(&dac33->mutex);
252 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
258 * D23..D16 dac33 register offset
269 if (dac33->chip_power) {
272 ret = i2c_master_send(dac33->i2c, data, 3);
284 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
286 if (unlikely(!dac33->chip_power))
365 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
368 mutex_lock(&dac33->mutex);
371 if (unlikely(power == dac33->chip_power)) {
378 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
379 dac33->supplies);
386 if (dac33->power_gpio >= 0)
387 gpio_set_value(dac33->power_gpio, 1);
389 dac33->chip_power = 1;
392 if (dac33->power_gpio >= 0)
393 gpio_set_value(dac33->power_gpio, 0);
395 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
396 dac33->supplies);
403 dac33->chip_power = 0;
407 mutex_unlock(&dac33->mutex);
415 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
419 if (likely(dac33->substream)) {
420 dac33_calculate_times(dac33->substream, component);
421 dac33_prepare_chip(dac33->substream, component);
435 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
437 ucontrol->value.enumerated.item[0] = dac33->fifo_mode;
446 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
449 if (dac33->fifo_mode == ucontrol->value.enumerated.item[0])
458 dac33->fifo_mode = ucontrol->value.enumerated.item[0];
645 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
647 struct snd_soc_component *component = dac33->component;
651 switch (dac33->fifo_mode) {
654 DAC33_THRREG(dac33->nsample));
657 spin_lock_irqsave(&dac33->lock, flags);
658 dac33->t_stamp2 = ktime_to_us(ktime_get());
659 dac33->t_stamp1 = dac33->t_stamp2;
660 spin_unlock_irqrestore(&dac33->lock, flags);
663 DAC33_THRREG(dac33->alarm_threshold));
665 delay = SAMPLES_TO_US(dac33->burst_rate,
666 dac33->alarm_threshold) + 1000;
672 spin_lock_irqsave(&dac33->lock, flags);
673 dac33->t_stamp1 = ktime_to_us(ktime_get());
675 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
676 spin_unlock_irqrestore(&dac33->lock, flags);
686 dac33->fifo_mode);
691 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
693 struct snd_soc_component *component = dac33->component;
696 switch (dac33->fifo_mode) {
699 spin_lock_irqsave(&dac33->lock, flags);
700 dac33->t_stamp2 = ktime_to_us(ktime_get());
701 spin_unlock_irqrestore(&dac33->lock, flags);
704 DAC33_THRREG(dac33->nsample));
711 dac33->fifo_mode);
719 struct tlv320dac33_priv *dac33;
722 dac33 = container_of(work, struct tlv320dac33_priv, work);
723 component = dac33->component;
725 mutex_lock(&dac33->mutex);
726 switch (dac33->state) {
728 dac33->state = DAC33_PLAYBACK;
729 dac33_prefill_handler(dac33);
732 dac33_playback_handler(dac33);
737 dac33->state = DAC33_IDLE;
738 /* Mask all interrupts from dac33 */
747 mutex_unlock(&dac33->mutex);
753 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
756 spin_lock_irqsave(&dac33->lock, flags);
757 dac33->t_stamp1 = ktime_to_us(ktime_get());
758 spin_unlock_irqrestore(&dac33->lock, flags);
761 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
762 schedule_work(&dac33->work);
785 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
788 dac33->substream = substream;
797 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
799 dac33->substream = NULL;
809 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
824 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
825 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
828 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
829 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
847 * writes happens in different order, than dac33 might end up in unknown state.
848 * Use the known, working sequence of register writes to initialize the dac33.
853 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
860 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
862 dac33->refclk);
892 mutex_lock(&dac33->mutex);
894 if (!dac33->chip_power) {
899 mutex_unlock(&dac33->mutex);
928 if (dac33->fifo_mode) {
947 switch (dac33->fifo_mode) {
963 switch (dac33->fifo_mode) {
973 if (dac33->keep_bclk)
987 if (dac33->keep_bclk)
1016 if (dac33->fifo_mode)
1018 dac33->burst_bclkdiv);
1025 switch (dac33->fifo_mode) {
1028 DAC33_THRREG(dac33->alarm_threshold));
1035 dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1043 mutex_unlock(&dac33->mutex);
1051 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1057 if (!dac33->fifo_mode)
1060 switch (dac33->fifo_mode) {
1063 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1064 dac33->mode1_latency);
1065 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1067 if (period_size <= dac33->alarm_threshold)
1072 dac33->nsample = period_size *
1073 ((dac33->alarm_threshold / period_size) +
1074 (dac33->alarm_threshold % period_size ?
1077 dac33->nsample = nsample_limit;
1079 dac33->nsample = period_size;
1081 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1082 dac33->nsample);
1083 dac33->t_stamp1 = 0;
1084 dac33->t_stamp2 = 0;
1087 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1088 dac33->burst_rate) + 9;
1089 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1090 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1091 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1092 dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1094 dac33->mode7_us_to_lthr =
1096 dac33->uthr - DAC33_MODE7_MARGIN + 1);
1097 dac33->t_stamp1 = 0;
1109 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1116 if (dac33->fifo_mode) {
1117 dac33->state = DAC33_PREFILL;
1118 schedule_work(&dac33->work);
1124 if (dac33->fifo_mode) {
1125 dac33->state = DAC33_FLUSH;
1126 schedule_work(&dac33->work);
1141 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1148 switch (dac33->fifo_mode) {
1152 spin_lock_irqsave(&dac33->lock, flags);
1153 t0 = dac33->t_stamp1;
1154 t1 = dac33->t_stamp2;
1155 spin_unlock_irqrestore(&dac33->lock, flags);
1172 if (likely(dac33->alarm_threshold > samples_out))
1173 delay = dac33->alarm_threshold - samples_out;
1176 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1188 dac33->burst_rate,
1191 samples = dac33->alarm_threshold;
1208 samples_in = dac33->nsample;
1209 samples = dac33->alarm_threshold;
1213 delay = samples > dac33->fifo_size ?
1214 dac33->fifo_size : samples;
1220 spin_lock_irqsave(&dac33->lock, flags);
1221 t0 = dac33->t_stamp1;
1222 uthr = dac33->uthr;
1223 spin_unlock_irqrestore(&dac33->lock, flags);
1240 if (time_delta <= dac33->mode7_us_to_lthr) {
1258 time_delta = time_delta - dac33->mode7_us_to_lthr;
1264 dac33->burst_rate,
1274 dac33->fifo_mode);
1285 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1303 dac33->refclk = freq;
1315 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1328 if (dac33->fifo_mode) {
1368 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1371 dac33->component = component;
1389 if (dac33->irq >= 0) {
1390 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1395 dac33->irq, ret);
1396 dac33->irq = -1;
1398 if (dac33->irq != -1) {
1399 INIT_WORK(&dac33->work, dac33_work);
1404 if (dac33->irq >= 0)
1414 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1416 if (dac33->irq >= 0) {
1417 free_irq(dac33->irq, dac33->component);
1418 flush_work(&dac33->work);
1470 struct tlv320dac33_priv *dac33;
1479 dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv),
1481 if (dac33 == NULL)
1484 dac33->reg_cache = devm_kmemdup(&client->dev,
1488 if (!dac33->reg_cache)
1491 dac33->i2c = client;
1492 mutex_init(&dac33->mutex);
1493 spin_lock_init(&dac33->lock);
1495 i2c_set_clientdata(client, dac33);
1497 dac33->power_gpio = pdata->power_gpio;
1498 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1499 dac33->keep_bclk = pdata->keep_bclk;
1500 dac33->mode1_latency = pdata->mode1_latency;
1501 if (!dac33->mode1_latency)
1502 dac33->mode1_latency = 10000; /* 10ms */
1503 dac33->irq = client->irq;
1505 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1508 if (dac33->power_gpio >= 0) {
1509 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1513 dac33->power_gpio);
1516 gpio_direction_output(dac33->power_gpio, 0);
1519 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1520 dac33->supplies[i].supply = dac33_supply_names[i];
1522 ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1523 dac33->supplies);
1537 if (dac33->power_gpio >= 0)
1538 gpio_free(dac33->power_gpio);
1545 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1547 if (unlikely(dac33->chip_power))
1548 dac33_hard_power(dac33->component, 0);
1550 if (dac33->power_gpio >= 0)
1551 gpio_free(dac33->power_gpio);