Lines Matching defs:rt5677
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
36 #include "rt5677.h"
37 #include "rt5677-spi.h"
555 * @rt5677: Private Data.
562 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
565 struct snd_soc_component *component = rt5677->component;
568 mutex_lock(&rt5677->dsp_cmd_lock);
570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
598 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
606 mutex_unlock(&rt5677->dsp_cmd_lock);
613 * @rt5677: Private Data.
621 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
623 struct snd_soc_component *component = rt5677->component;
627 mutex_lock(&rt5677->dsp_cmd_lock);
629 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
636 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
643 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
650 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
651 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
655 mutex_unlock(&rt5677->dsp_cmd_lock);
662 * @rt5677: Private Data.
669 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
672 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
678 * @rt5677: Private Data
686 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
688 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
696 static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on)
699 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
701 rt5677->is_dsp_mode = true;
703 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
705 rt5677->is_dsp_mode = false;
709 static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677)
712 snd_soc_component_get_dapm(rt5677->component);
721 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
725 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
729 regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
733 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
735 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
740 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
753 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
766 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
772 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
779 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
789 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
802 regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
813 static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf,
816 struct snd_soc_component *component = rt5677->component;
857 static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677)
860 struct device *dev = rt5677->component->dev;
871 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
878 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
879 rt5677->dsp_vad_en_request = on;
880 rt5677->dsp_vad_en = on;
885 schedule_delayed_work(&rt5677->dsp_work, 0);
891 struct rt5677_priv *rt5677 =
894 bool enable = rt5677->dsp_vad_en;
898 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
914 rt5677_set_vad_source(rt5677);
915 rt5677_set_dsp_mode(rt5677, true);
919 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
925 dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
930 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
932 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
934 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
937 rt5677_load_dsp_from_file(rt5677);
940 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
946 mutex_lock(&rt5677->irq_lock);
948 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
951 rt5677_set_dsp_mode(rt5677, false);
954 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);
957 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
960 mutex_unlock(&rt5677->irq_lock);
984 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
986 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
1091 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1094 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
1100 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
1109 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1112 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
1124 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1191 regmap_read(rt5677->regmap, reg, &val);
1207 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1209 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1232 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1280 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1309 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1338 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1355 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1372 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1401 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1412 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1417 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1423 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1429 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1435 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1441 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1447 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
2573 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2577 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2582 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2597 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2601 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2606 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2621 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2625 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2629 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2643 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2647 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2651 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2665 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2669 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2676 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2692 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2697 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2699 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2715 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2720 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2722 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2738 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2743 !rt5677->is_vref_slow) {
2745 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2748 rt5677->is_vref_slow = true;
4293 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4297 rt5677->lrck[dai->id] = params_rate(params);
4298 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4301 rt5677->sysclk, rt5677->lrck[dai->id]);
4310 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4313 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4337 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4339 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4345 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4347 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4354 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4356 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4363 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4365 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4378 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4383 rt5677->master[dai->id] = 1;
4387 rt5677->master[dai->id] = 0;
4421 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4426 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4431 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4436 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4452 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4455 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4472 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4474 rt5677->sysclk = freq;
4475 rt5677->sysclk_src = clk_id;
4505 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4509 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4510 freq_out == rt5677->pll_out)
4516 rt5677->pll_in = 0;
4517 rt5677->pll_out = 0;
4518 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4525 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4534 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4538 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4542 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4546 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4570 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4574 rt5677->pll_in = freq_in;
4575 rt5677->pll_out = freq_out;
4576 rt5677->pll_src = source;
4585 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4626 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4628 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4632 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4634 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4647 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4658 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4662 regmap_update_bits(rt5677->regmap,
4665 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4671 rt5677->is_vref_slow = false;
4672 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4674 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4681 rt5677->dsp_vad_en_request) {
4683 rt5677->dsp_vad_en = true;
4685 schedule_delayed_work(&rt5677->dsp_work,
4691 flush_delayed_work(&rt5677->dsp_work);
4692 if (rt5677->is_dsp_mode) {
4694 rt5677->dsp_vad_en = false;
4695 schedule_delayed_work(&rt5677->dsp_work, 0);
4696 flush_delayed_work(&rt5677->dsp_work);
4699 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4700 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4701 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
4704 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4706 regmap_update_bits(rt5677->regmap,
4709 if (rt5677->dsp_vad_en)
4723 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4727 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4732 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4744 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4748 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4754 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4768 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4771 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4780 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4784 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4789 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4805 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4813 regmap_update_bits(rt5677->regmap,
4821 regmap_update_bits(rt5677->regmap,
4834 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4837 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4838 (rt5677->pdata.jd1_gpio == 2 &&
4840 (rt5677->pdata.jd1_gpio == 3 &&
4843 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4844 (rt5677->pdata.jd2_gpio == 2 &&
4846 (rt5677->pdata.jd2_gpio == 3 &&
4849 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4851 (rt5677->pdata.jd3_gpio == 2 &&
4853 (rt5677->pdata.jd3_gpio == 3 &&
4860 return irq_create_mapping(rt5677->domain, irq);
4876 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4879 rt5677->gpio_chip = rt5677_template_chip;
4880 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4881 rt5677->gpio_chip.parent = &i2c->dev;
4882 rt5677->gpio_chip.base = -1;
4884 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4891 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4893 gpiochip_remove(&rt5677->gpio_chip);
4896 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4913 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4916 rt5677->component = component;
4918 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4930 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4932 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
4936 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4938 mutex_init(&rt5677->dsp_cmd_lock);
4939 mutex_init(&rt5677->dsp_pri_lock);
4946 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4948 cancel_delayed_work_sync(&rt5677->dsp_work);
4950 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4951 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4952 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4958 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4960 if (rt5677->irq) {
4961 cancel_delayed_work_sync(&rt5677->resume_irq_check);
4962 disable_irq(rt5677->irq);
4965 if (!rt5677->dsp_vad_en) {
4966 regcache_cache_only(rt5677->regmap, true);
4967 regcache_mark_dirty(rt5677->regmap);
4969 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4970 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4978 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4980 if (!rt5677->dsp_vad_en) {
4981 rt5677->pll_src = 0;
4982 rt5677->pll_in = 0;
4983 rt5677->pll_out = 0;
4984 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4985 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4986 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4989 regcache_cache_only(rt5677->regmap, false);
4990 regcache_sync(rt5677->regmap);
4993 if (rt5677->irq) {
4994 enable_irq(rt5677->irq);
4995 schedule_delayed_work(&rt5677->resume_irq_check, 0);
5008 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
5010 if (rt5677->is_dsp_mode) {
5012 mutex_lock(&rt5677->dsp_pri_lock);
5013 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
5015 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
5016 mutex_unlock(&rt5677->dsp_pri_lock);
5018 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
5021 regmap_read(rt5677->regmap_physical, reg, val);
5030 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
5032 if (rt5677->is_dsp_mode) {
5034 mutex_lock(&rt5677->dsp_pri_lock);
5035 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
5037 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
5039 mutex_unlock(&rt5677->dsp_pri_lock);
5041 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
5044 regmap_write(rt5677->regmap_physical, reg, val);
5069 .name = "rt5677-aif1",
5088 .name = "rt5677-aif2",
5107 .name = "rt5677-aif3",
5126 .name = "rt5677-aif4",
5145 .name = "rt5677-slimbus",
5164 .name = "rt5677-dspbuffer",
5229 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
5240 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5245 rt5677->pdata.in1_diff =
5249 rt5677->pdata.in2_diff =
5253 rt5677->pdata.lout1_diff =
5257 rt5677->pdata.lout2_diff =
5261 rt5677->pdata.lout3_diff =
5266 rt5677->pdata.gpio_config,
5271 rt5677->pdata.dmic2_clk_pin = val;
5275 rt5677->pdata.jd1_gpio = val;
5279 rt5677->pdata.jd2_gpio = val;
5283 rt5677->pdata.jd3_gpio = val;
5310 static bool rt5677_check_hotword(struct rt5677_priv *rt5677)
5314 if (!rt5677->is_dsp_mode)
5317 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio))
5325 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5334 struct rt5677_priv *rt5677 = data;
5338 mutex_lock(&rt5677->irq_lock);
5356 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq);
5358 dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
5367 virq = irq_find_mapping(rt5677->domain, i);
5383 if (!irq_fired && !rt5677_check_hotword(rt5677))
5386 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
5388 dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
5395 mutex_unlock(&rt5677->irq_lock);
5405 struct rt5677_priv *rt5677 =
5413 rt5677_irq(0, rt5677);
5424 mutex_lock(&rt5677->irq_lock);
5426 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) {
5427 virq = irq_find_mapping(rt5677->domain, i);
5432 mutex_unlock(&rt5677->irq_lock);
5437 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5439 mutex_lock(&rt5677->irq_lock);
5444 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5447 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
5449 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
5450 mutex_unlock(&rt5677->irq_lock);
5455 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5457 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
5462 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5464 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
5478 struct rt5677_priv *rt5677 = h->host_data;
5480 irq_set_chip_data(virq, rt5677);
5496 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5499 if (!rt5677->pdata.jd1_gpio &&
5500 !rt5677->pdata.jd2_gpio &&
5501 !rt5677->pdata.jd3_gpio)
5509 mutex_init(&rt5677->irq_lock);
5510 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check);
5517 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
5521 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
5524 if (rt5677->pdata.jd1_gpio) {
5526 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
5528 if (rt5677->pdata.jd2_gpio) {
5530 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
5532 if (rt5677->pdata.jd3_gpio) {
5534 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
5536 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
5539 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5543 rt5677->domain = irq_domain_add_linear(i2c->dev.of_node,
5544 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677);
5545 if (!rt5677->domain) {
5552 "rt5677", rt5677);
5556 rt5677->irq = i2c->irq;
5563 struct rt5677_priv *rt5677;
5567 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5569 if (rt5677 == NULL)
5572 rt5677->dev = &i2c->dev;
5573 rt5677->set_dsp_vad = rt5677_set_dsp_vad;
5574 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work);
5575 i2c_set_clientdata(i2c, rt5677);
5582 rt5677->type = (enum rt5677_type)match_id->data;
5588 rt5677->type = (enum rt5677_type)acpi_id->driver_data;
5593 rt5677_read_device_properties(rt5677, &i2c->dev);
5599 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5601 if (IS_ERR(rt5677->pow_ldo2)) {
5602 ret = PTR_ERR(rt5677->pow_ldo2);
5606 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5608 if (IS_ERR(rt5677->reset_pin)) {
5609 ret = PTR_ERR(rt5677->reset_pin);
5614 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5622 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5624 if (IS_ERR(rt5677->regmap_physical)) {
5625 ret = PTR_ERR(rt5677->regmap_physical);
5631 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5632 if (IS_ERR(rt5677->regmap)) {
5633 ret = PTR_ERR(rt5677->regmap);
5639 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5642 "Device with ID register %#x is not rt5677\n", val);
5646 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5648 ret = regmap_register_patch(rt5677->regmap, init_list,
5653 if (rt5677->pdata.in1_diff)
5654 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5657 if (rt5677->pdata.in2_diff)
5658 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5661 if (rt5677->pdata.lout1_diff)
5662 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5665 if (rt5677->pdata.lout2_diff)
5666 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5669 if (rt5677->pdata.lout3_diff)
5670 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5673 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5674 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5677 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5682 if (rt5677->pdata.micbias1_vdd_3v3)
5683 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,