Lines Matching defs:nau8540
27 #include "nau8540.h"
237 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
242 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
244 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
247 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
249 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
259 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
262 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
263 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
360 static int nau8540_clock_check(struct nau8540 *nau8540, int rate, int osr)
366 dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n");
377 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
386 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
388 if (nau8540_clock_check(nau8540, params_rate(params), osr))
390 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
411 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
420 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
464 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
467 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
469 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
491 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
504 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
507 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
509 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
528 .name = "nau8540-hifi",
649 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
655 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
661 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
668 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
675 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
678 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
684 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
687 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
691 nau8540_fll_apply(nau8540->regmap, &fll_param);
693 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
702 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
707 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
709 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
714 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
716 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
721 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
725 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
737 static void nau8540_init_regs(struct nau8540 *nau8540)
739 struct regmap *regmap = nau8540->regmap;
776 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
778 regcache_cache_only(nau8540->regmap, true);
779 regcache_mark_dirty(nau8540->regmap);
786 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
788 regcache_cache_only(nau8540->regmap, false);
789 regcache_sync(nau8540->regmap);
830 struct nau8540 *nau8540 = dev_get_platdata(dev);
833 if (!nau8540) {
834 nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
835 if (!nau8540)
838 i2c_set_clientdata(i2c, nau8540);
840 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
841 if (IS_ERR(nau8540->regmap))
842 return PTR_ERR(nau8540->regmap);
843 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
850 nau8540->dev = dev;
851 nau8540_reset_chip(nau8540->regmap);
852 nau8540_init_regs(nau8540);
859 { "nau8540", 0 },
866 { .compatible = "nuvoton,nau8540", },
874 .name = "nau8540",