Lines Matching refs:x7
288 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
289 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
291 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
292 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
319 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
320 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
322 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
323 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
407 #define CCI_AUDIO_FIFO_WPTR_MASK 0x7
408 #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)
482 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
483 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
485 #define SDM_TESTCK_SRC_SEL_MASK 0x7
486 #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)
488 #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7
489 #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)
511 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
512 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
547 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK 0x7
548 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 10)
568 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
569 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
590 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK 0x7
591 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT (0x7 << 12)
823 #define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7
824 #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
826 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7
827 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
871 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
872 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
879 #define RG_MTKAIF_RX_SYNC_WORD2_MASK 0x7
880 #define RG_MTKAIF_RX_SYNC_WORD2_MASK_SFT (0x7 << 4)
882 #define RG_MTKAIF_RX_SYNC_WORD1_MASK 0x7
883 #define RG_MTKAIF_RX_SYNC_WORD1_MASK_SFT (0x7 << 0)
887 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK 0x7
888 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 12)
890 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK 0x7
891 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 8)
893 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK 0x7
894 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 4)
896 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK 0x7
897 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 0)
1007 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7
1008 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)
1125 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK 0x7
1126 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT (0x7 << 4)
1128 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK 0x7
1129 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT (0x7 << 1)
1173 #define RG_AUDPREAMPLGAIN_MASK 0x7
1174 #define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)
1205 #define RG_AUDPREAMPRGAIN_MASK 0x7
1206 #define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)
1237 #define RG_AUDPREAMP3GAIN_MASK 0x7
1238 #define RG_AUDPREAMP3GAIN_MASK_SFT (0x7 << 8)
1478 #define RG_DMICMONSEL_MASK 0x7
1479 #define RG_DMICMONSEL_MASK_SFT (0x7 << 9)
1501 #define RG_DMIC1MONSEL_MASK 0x7
1502 #define RG_DMIC1MONSEL_MASK_SFT (0x7 << 9)
1521 #define RG_AUDMICBIAS0VREF_MASK 0x7
1522 #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)
1553 #define RG_AUDMICBIAS1VREF_MASK 0x7
1554 #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
1582 #define RG_AUDMICBIAS2VREF_MASK 0x7
1583 #define RG_AUDMICBIAS2VREF_MASK_SFT (0x7 << 4)
1699 #define RG_EINT0CTURBO_MASK 0x7
1700 #define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)
1717 #define RG_EINT1CTURBO_MASK 0x7
1718 #define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)
1756 #define RG_SPARE_VOW_MASK 0x7
1757 #define RG_SPARE_VOW_MASK_SFT (0x7 << 7)
1829 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK 0x7
1830 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 8)
1832 #define RG_HPROUTSTGCTRL_VAUDP32_MASK 0x7
1833 #define RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 12)
1837 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x7
1838 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)
1840 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x7
1841 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)
1858 #define RG_HPPSHORT2VCM_VAUDP32_MASK 0x7
1859 #define RG_HPPSHORT2VCM_VAUDP32_MASK_SFT (0x7 << 12)
1869 #define RG_AUDHPLFINETRIM_VAUDP32_MASK 0x7
1870 #define RG_AUDHPLFINETRIM_VAUDP32_MASK_SFT (0x7 << 5)
1875 #define RG_AUDHPRFINETRIM_VAUDP32_MASK 0x7
1876 #define RG_AUDHPRFINETRIM_VAUDP32_MASK_SFT (0x7 << 13)
1880 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK 0x7
1881 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK_SFT (0x7 << 0)
1883 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK 0x7
1884 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 4)
1886 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK 0x7
1887 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 8)
1897 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK 0x7
1898 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK_SFT (0x7 << 0)
1900 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK 0x7
1901 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK_SFT (0x7 << 4)
2017 #define RG_AUDZCDMUXSEL_VAUDP32_MASK 0x7
2018 #define RG_AUDZCDMUXSEL_VAUDP32_MASK_SFT (0x7 << 0)
2079 #define RG_AUDZCDGAINSTEPTIME_MASK 0x7
2080 #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)
2111 #define RG_AUDIVLGAIN_MASK 0x7
2112 #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)
2114 #define RG_AUDIVRGAIN_MASK 0x7
2115 #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)
2362 #define DRBIAS_MASK 0x7
2449 HP_MUX_MASK = 0x7,