Lines Matching defs:component
310 static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai,
328 snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i]));
329 snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i]));
383 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
384 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
388 snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
397 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
398 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
407 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
408 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
412 snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
421 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
422 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
620 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
621 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
626 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
629 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
634 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0);
650 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
651 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
671 snd_soc_component_update_bits(component, w->reg,
677 snd_soc_component_update_bits(component, w->reg,
966 struct snd_soc_component *component = dai->component;
967 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
979 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
983 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
990 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
995 snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE,
1000 if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT)
1005 dev_err(component->dev, "Invalid system clock frequency\n");
1012 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
1014 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
1020 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1023 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1026 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1036 struct snd_soc_component *component = dai->component;
1037 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1049 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1053 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1060 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1065 snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE,
1070 if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT)
1075 dev_err(component->dev, "Invalid system clock frequency\n");
1082 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1084 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1090 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1093 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1096 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1105 struct snd_soc_component *component = dai->component;
1106 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1122 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);
1125 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);
1128 dev_err(component->dev, "Invalid master clock frequency\n");
1132 if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1133 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1135 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1148 struct snd_soc_component *component = codec_dai->component;
1149 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1162 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
1164 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
1174 dev_err(component->dev, "Clock mode unsupported");
1204 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
1211 snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val);
1220 struct snd_soc_component *component = codec_dai->component;
1221 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1233 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1235 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1245 dev_err(component->dev, "Clock mode unsupported");
1275 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1279 snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK,
1289 struct snd_soc_component *component = codec_dai->component;
1297 snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY,
1305 struct snd_soc_component *component = codec_dai->component;
1313 snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY,
1318 static int max98088_set_bias_level(struct snd_soc_component *component,
1321 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1336 if (snd_soc_component_get_bias_level(component) ==
1345 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
1348 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1353 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1414 static int max98088_get_channel(struct snd_soc_component *component, const char *name)
1420 dev_err(component->dev, "Bad EQ channel name '%s'\n", name);
1424 static void max98088_setup_eq1(struct snd_soc_component *component)
1426 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1451 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1456 save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
1457 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1461 m98088_eq_band(component, 0, 0, coef_set->band1);
1462 m98088_eq_band(component, 0, 1, coef_set->band2);
1463 m98088_eq_band(component, 0, 2, coef_set->band3);
1464 m98088_eq_band(component, 0, 3, coef_set->band4);
1465 m98088_eq_band(component, 0, 4, coef_set->band5);
1468 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1471 static void max98088_setup_eq2(struct snd_soc_component *component)
1473 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1498 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1503 save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
1504 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1508 m98088_eq_band(component, 1, 0, coef_set->band1);
1509 m98088_eq_band(component, 1, 1, coef_set->band2);
1510 m98088_eq_band(component, 1, 2, coef_set->band3);
1511 m98088_eq_band(component, 1, 3, coef_set->band4);
1512 m98088_eq_band(component, 1, 4, coef_set->band5);
1515 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1522 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1523 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1525 int channel = max98088_get_channel(component, kcontrol->id.name);
1541 max98088_setup_eq1(component);
1544 max98088_setup_eq2(component);
1554 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1555 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1556 int channel = max98088_get_channel(component, kcontrol->id.name);
1567 static void max98088_handle_eq_pdata(struct snd_soc_component *component)
1569 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1622 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1624 dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1627 static void max98088_handle_pdata(struct snd_soc_component *component)
1629 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1634 dev_dbg(component->dev, "No platform data\n");
1647 snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval);
1651 snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL,
1656 max98088_handle_eq_pdata(component);
1659 static int max98088_probe(struct snd_soc_component *component)
1661 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1689 ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID);
1691 dev_err(component->dev, "Failed to read device revision: %d\n",
1695 dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A');
1697 snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1699 snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00);
1701 snd_soc_component_write(component, M98088_REG_22_MIX_DAC,
1705 snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0);
1706 snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F);
1708 snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG,
1711 snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG,
1714 max98088_handle_pdata(component);
1720 static void max98088_remove(struct snd_soc_component *component)
1722 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);