Lines Matching defs:rate
908 * We don't directly write the rate register here but we want to
909 * maintain consistent behaviour that rate domains cannot be changed
1021 * the rate domain control.
1030 "Failed to read current DSP rate: %d\n", ret);
1039 dev_dbg(madera->dev, "DSP rate not changed\n");
1042 dev_dbg(madera->dev, "DSP rate changed\n");
1069 * safe to change rate domain
1627 "SYNCCLK rate 1", "SYNCCLK rate 2", "SYNCCLK rate 3",
1628 "ASYNCCLK rate 1", "ASYNCCLK rate 2",
2629 int div, div_inc, rate;
2651 rate = 5644800;
2653 rate = 6144000;
2658 if (freq / div == rate && !(freq % div)) {
2659 dev_dbg(component->dev, "Configured %dHz OUTCLK\n", rate);
2674 rate, freq);
3008 madera_aif_err(dai, "Unsupported sample rate %dHz\n",
3049 madera_aif_err(dai, "Failed to check rate: %d\n", ret);
3059 madera_aif_warn(dai, "Cannot change rate while active\n");
3064 /* Guard the rate change with SYSCLK cycles */
3109 unsigned int rate = params_rate(params);
3118 if (rate % 4000) {
3131 bclk_target = tdm_slots * tdm_width * rate;
3154 if (rates[i] >= bclk_target && rates[i] % rate == 0) {
3161 madera_aif_err(dai, "Unsupported sample rate %dHz\n", rate);
3165 lrclk = rates[bclk] / rate;
4659 * provided in the form of the required sysclk rate, which is