Lines Matching defs:cs43130
3 * cs43130.c -- CS43130 ALSA Soc Audio driver
38 #include "cs43130.h"
238 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
241 dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n",
242 cs43130->mclk, cs43130->mclk_int);
244 pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int);
249 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
252 cs43130->pll_bypass = true;
256 cs43130->pll_bypass = false;
258 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2,
262 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3,
266 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4,
270 regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
272 regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout);
273 regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
275 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
278 regmap_write(cs43130->regmap, CS43130_PLL_SET_9,
280 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
290 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
303 cs43130->mclk = freq_in;
313 cs43130->mclk_int = freq_out;
316 cs43130->mclk_int = freq_out;
325 dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass);
333 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
336 if (src == cs43130->mclk_int_src) {
341 switch (cs43130->mclk_int) {
349 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int);
355 cs43130->pll_bypass = true;
356 cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT;
357 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
358 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
362 reinit_completion(&cs43130->xtal_rdy);
363 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
365 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
367 ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
369 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
378 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
381 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
386 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
391 cs43130->pll_bypass = false;
392 cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL;
393 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
394 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
398 reinit_completion(&cs43130->xtal_rdy);
399 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
401 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
403 ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
405 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
414 reinit_completion(&cs43130->pll_rdy);
415 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
417 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
419 ret = wait_for_completion_timeout(&cs43130->pll_rdy,
421 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
429 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
432 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
438 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
440 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
443 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
448 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
451 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
558 struct cs43130_private *cs43130)
573 switch (cs43130->dais[dai_id].dai_format) {
598 switch (cs43130->dais[dai_id].dai_mode) {
631 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
634 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
637 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
640 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
643 regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data);
644 regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1);
645 regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2);
646 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
648 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
650 regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data);
653 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1,
656 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2,
659 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1,
662 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2,
665 regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data);
666 regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1);
667 regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2);
668 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN,
670 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN,
672 regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data);
680 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
686 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
692 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
698 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
713 regmap_write(cs43130->regmap, CS43130_ASP_DEN_1,
716 regmap_write(cs43130->regmap, CS43130_ASP_DEN_2,
719 regmap_write(cs43130->regmap, CS43130_ASP_NUM_1,
722 regmap_write(cs43130->regmap, CS43130_ASP_NUM_2,
727 regmap_write(cs43130->regmap, CS43130_XSP_DEN_1,
730 regmap_write(cs43130->regmap, CS43130_XSP_DEN_2,
733 regmap_write(cs43130->regmap, CS43130_XSP_NUM_1,
736 regmap_write(cs43130->regmap, CS43130_XSP_NUM_2,
775 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
779 mutex_lock(&cs43130->clk_mutex);
780 if (!cs43130->clk_req) {
787 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
788 if (cs43130->pll_bypass)
794 cs43130->clk_req++;
795 if (cs43130->clk_req == 2)
796 cs43130_pcm_dsd_mix(true, cs43130->regmap);
797 mutex_unlock(&cs43130->clk_mutex);
812 if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
813 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
816 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
819 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
822 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
834 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
836 unsigned int sclk = cs43130->dais[dai->id].sclk;
842 mutex_lock(&cs43130->clk_mutex);
843 if (!cs43130->clk_req) {
850 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
851 if (cs43130->pll_bypass)
857 cs43130->clk_req++;
858 if (cs43130->clk_req == 2)
859 cs43130_pcm_dsd_mix(true, cs43130->regmap);
860 mutex_unlock(&cs43130->clk_mutex);
883 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
892 regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val);
901 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
906 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
912 if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
937 cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap);
938 cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130);
947 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
949 mutex_lock(&cs43130->clk_mutex);
950 cs43130->clk_req--;
951 if (!cs43130->clk_req) {
954 cs43130_pcm_dsd_mix(false, cs43130->regmap);
956 mutex_unlock(&cs43130->clk_mutex);
1024 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1031 switch (cs43130->dev_id) {
1035 regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq,
1038 regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq,
1145 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1149 switch (cs43130->dev_id) {
1152 regmap_multi_reg_write(cs43130->regmap, dsd_seq,
1158 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1,
1160 switch (cs43130->dev_id) {
1163 regmap_multi_reg_write(cs43130->regmap, unmute_seq,
1169 switch (cs43130->dev_id) {
1172 regmap_multi_reg_write(cs43130->regmap, mute_seq,
1174 regmap_update_bits(cs43130->regmap,
1185 regmap_update_bits(cs43130->regmap,
1202 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1206 switch (cs43130->dev_id) {
1209 regmap_multi_reg_write(cs43130->regmap, pcm_seq,
1215 regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
1217 switch (cs43130->dev_id) {
1220 regmap_multi_reg_write(cs43130->regmap, unmute_seq,
1226 switch (cs43130->dev_id) {
1229 regmap_multi_reg_write(cs43130->regmap, mute_seq,
1231 regmap_update_bits(cs43130->regmap,
1242 regmap_update_bits(cs43130->regmap,
1271 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1275 switch (cs43130->dev_id) {
1278 regmap_multi_reg_write(cs43130->regmap, pop_free_seq,
1283 regmap_multi_reg_write(cs43130->regmap, pop_free_seq2,
1291 regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
1293 switch (cs43130->dev_id) {
1296 regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq,
1304 regmap_write(cs43130->regmap, CS43130_DXD12, 0);
1309 regmap_write(cs43130->regmap, CS43130_DXD13, 0);
1313 regmap_write(cs43130->regmap, CS43130_DXD1, 0);
1316 switch (cs43130->dev_id) {
1319 regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq,
1351 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1355 regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq,
1359 regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq,
1472 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1476 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
1479 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
1488 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S;
1491 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J;
1494 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A;
1497 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B;
1507 cs43130->dais[codec_dai->id].dai_mode,
1508 cs43130->dais[codec_dai->id].dai_format);
1516 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1520 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
1523 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
1531 cs43130->dais[codec_dai->id].dai_mode);
1540 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1542 cs43130->dais[codec_dai->id].sclk = freq;
1544 cs43130->dais[codec_dai->id].sclk);
1574 .name = "cs43130-asp-pcm",
1587 .name = "cs43130-asp-dop",
1600 .name = "cs43130-xsp-dop",
1613 .name = "cs43130-xsp-dsd",
1631 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1639 cs43130->mclk = freq;
1647 cs43130->pll_bypass = true;
1665 struct cs43130_private *cs43130 = i2c_get_clientdata(client);
1667 if (!cs43130->hpload_done)
1671 cs43130->hpload_dc[ch]);
1703 struct cs43130_private *cs43130 = i2c_get_clientdata(client);
1705 if (cs43130->hpload_done && cs43130->ac_meas) {
1708 cs43130->hpload_ac[i][ch]);
1931 struct cs43130_private *cs43130)
1937 struct snd_soc_component *component = cs43130->component;
1947 regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®);
1956 regmap_read(cs43130->regmap, addr, ®);
1958 regmap_read(cs43130->regmap, addr + 1, ®);
1963 cs43130->hpload_dc[HP_LEFT] = impedance;
1965 cs43130->hpload_dc[HP_RIGHT] = impedance;
1971 cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance;
1973 cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance;
1976 cs43130->ac_freq[ac_idx], !left_ch, impedance);
1982 static int cs43130_hpload_proc(struct cs43130_private *cs43130,
1989 struct snd_soc_component *component = cs43130->component;
1991 reinit_completion(&cs43130->hpload_evt);
1994 ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]);
1995 regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1,
1997 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1,
2000 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2,
2005 regmap_multi_reg_write(cs43130->regmap, seq,
2008 ret = wait_for_completion_timeout(&cs43130->hpload_evt,
2010 regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk);
2017 cs43130->hpload_stat, msk);
2018 if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT |
2021 !(cs43130->hpload_stat & rslt_msk)) {
2063 struct cs43130_private *cs43130;
2067 cs43130 = container_of(wk, struct cs43130_private, work);
2068 component = cs43130->component;
2070 if (!cs43130->mclk)
2073 cs43130->hpload_done = false;
2075 mutex_lock(&cs43130->clk_mutex);
2076 if (!cs43130->clk_req) {
2078 cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M);
2079 if (cs43130->pll_bypass)
2085 cs43130->clk_req++;
2086 mutex_unlock(&cs43130->clk_mutex);
2088 regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®);
2090 switch (cs43130->dev_id) {
2100 WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id);
2107 ret = cs43130_hpload_proc(cs43130, hpload_seq[i].seq,
2113 cs43130_update_hpload(hpload_seq[i].msk, ac_idx, cs43130);
2115 if (cs43130->ac_meas &&
2124 cs43130->hpload_done = true;
2126 if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD)
2127 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT,
2130 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE,
2136 cs43130->dc_threshold[i]);
2138 cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT],
2139 cs43130->dc_threshold);
2142 switch (cs43130->dev_id) {
2144 cs43130_hpload_proc(cs43130, hp_dis_cal_seq,
2149 cs43130_hpload_proc(cs43130, hp_dis_cal_seq2,
2155 regmap_multi_reg_write(cs43130->regmap, hp_cln_seq,
2158 mutex_lock(&cs43130->clk_mutex);
2159 cs43130->clk_req--;
2161 if (!cs43130->clk_req)
2163 mutex_unlock(&cs43130->clk_mutex);
2168 struct cs43130_private *cs43130 = (struct cs43130_private *)data;
2169 struct snd_soc_component *component = cs43130->component;
2176 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i,
2178 regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i,
2194 complete(&cs43130->xtal_rdy);
2199 complete(&cs43130->pll_rdy);
2204 cs43130->hpload_stat = stickies[3];
2207 cs43130->hpload_stat);
2208 complete(&cs43130->hpload_evt);
2213 cs43130->hpload_stat = stickies[3];
2215 cs43130->hpload_stat);
2216 complete(&cs43130->hpload_evt);
2221 cs43130->hpload_stat = stickies[3];
2223 cs43130->hpload_stat);
2224 complete(&cs43130->hpload_evt);
2229 cs43130->hpload_stat = stickies[3];
2231 cs43130->hpload_stat);
2232 complete(&cs43130->hpload_evt);
2237 cs43130->hpload_stat = stickies[3];
2239 cs43130->hpload_stat);
2240 complete(&cs43130->hpload_evt);
2245 cs43130->hpload_stat = stickies[3];
2247 cs43130->hpload_stat);
2248 complete(&cs43130->hpload_evt);
2253 cs43130->hpload_stat = stickies[3];
2255 cs43130->hpload_stat);
2256 complete(&cs43130->hpload_evt);
2267 cs43130->hpload_done = false;
2268 snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK);
2273 if (cs43130->dc_meas && !cs43130->hpload_done &&
2274 !work_busy(&cs43130->work)) {
2276 queue_work(cs43130->wq, &cs43130->work);
2279 snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL,
2290 struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
2294 cs43130->component = component;
2296 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) {
2297 regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET,
2299 cs43130->xtal_ibias);
2300 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2305 &cs43130->jack, NULL, 0);
2311 cs43130->hpload_done = false;
2312 if (cs43130->dc_meas) {
2317 cs43130->wq = create_singlethread_workqueue("cs43130_hp");
2318 if (!cs43130->wq) {
2322 INIT_WORK(&cs43130->work, cs43130_imp_meas);
2325 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®);
2326 regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®);
2327 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2329 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
2331 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
2373 struct cs43130_private *cs43130)
2381 cs43130->xtal_ibias = CS43130_XTAL_UNUSED;
2387 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
2390 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
2393 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
2401 cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure");
2402 cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure");
2404 if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq,
2407 cs43130->ac_freq[i] = cs43130_ac_freq[i];
2411 cs43130->dc_threshold,
2414 cs43130->dc_threshold[i] = cs43130_dc_threshold[i];
2423 struct cs43130_private *cs43130;
2429 cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
2430 if (!cs43130)
2433 i2c_set_clientdata(client, cs43130);
2435 cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
2436 if (IS_ERR(cs43130->regmap)) {
2437 ret = PTR_ERR(cs43130->regmap);
2442 ret = cs43130_handle_device_data(client, cs43130);
2446 for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
2447 cs43130->supplies[i].supply = cs43130_supply_names[i];
2450 ARRAY_SIZE(cs43130->supplies),
2451 cs43130->supplies);
2456 ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
2457 cs43130->supplies);
2463 cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
2465 if (IS_ERR(cs43130->reset_gpio))
2466 return PTR_ERR(cs43130->reset_gpio);
2468 gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
2472 ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, ®);
2475 ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, ®);
2477 ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, ®);
2495 cs43130->dev_id = devid;
2496 ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®);
2506 mutex_init(&cs43130->clk_mutex);
2508 init_completion(&cs43130->xtal_rdy);
2509 init_completion(&cs43130->pll_rdy);
2510 init_completion(&cs43130->hpload_evt);
2515 "cs43130", cs43130);
2521 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
2528 switch (cs43130->dev_id) {
2571 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
2573 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
2583 struct cs43130_private *cs43130 = i2c_get_clientdata(client);
2585 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2586 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2590 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2594 if (cs43130->dc_meas) {
2595 cancel_work_sync(&cs43130->work);
2596 flush_workqueue(cs43130->wq);
2604 gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
2607 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2614 struct cs43130_private *cs43130 = dev_get_drvdata(dev);
2616 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2617 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2621 regcache_cache_only(cs43130->regmap, true);
2622 regcache_mark_dirty(cs43130->regmap);
2624 gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
2626 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2633 struct cs43130_private *cs43130 = dev_get_drvdata(dev);
2636 ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2642 regcache_cache_only(cs43130->regmap, false);
2644 gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
2648 ret = regcache_sync(cs43130->regmap);
2654 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2655 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2660 regcache_cache_only(cs43130->regmap, true);
2661 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2672 {.compatible = "cirrus,cs43130",},
2682 {"cs43130", 0},
2693 .name = "cs43130",