Lines Matching defs:value
256 u32 value, fci_id;
261 value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
262 value &= ~I2S_STREAM_CFG_MASK;
269 value |= aio->portnum << I2S_OUT_STREAM_CFG_GROUP_ID;
270 value |= aio->portnum; /* FCI ID is the port num */
271 value |= CH_GRP_STEREO << I2S_OUT_STREAM_CFG_CHANNEL_GROUPING;
272 writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
275 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
276 value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
277 value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
278 value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
279 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
282 value = readl(aio->cygaud->i2s_in +
284 value &= ~I2S_CAP_STREAM_CFG_MASK;
285 value |= aio->portnum << I2S_IN_STREAM_CFG_0_GROUP_ID;
286 writel(value, aio->cygaud->i2s_in +
292 value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
293 value |= BIT(BF_DST_CFGX_DFIFO_SZ_DOUBLE);
294 value &= ~BIT(BF_DST_CFGX_NOT_PAUSE_WHEN_FULL);
295 value |= (fci_id << BF_DST_CFGX_FCI_ID);
296 value |= BIT(BF_DST_CFGX_PROC_SEQ_ID_VALID);
297 writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
300 value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
301 value &= ~BIT((aio->portnum * 4) + AUD_MISC_SEROUT_SDAT_OE);
302 writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
307 value = readl(aio->cygaud->audio + SPDIF_CTRL_OFFSET);
308 value |= BIT(SPDIF_0_OUT_DITHER_ENA);
309 writel(value, aio->cygaud->audio + SPDIF_CTRL_OFFSET);
312 value = readl(aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
313 value &= ~SPDIF_STREAM_CFG_MASK;
314 value |= aio->portnum; /* FCI ID is the port num */
315 value |= BIT(SPDIF_0_OUT_STREAM_ENA);
316 writel(value, aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
318 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
319 value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
320 value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
321 value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
322 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
325 value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
326 value &= ~BIT(AUD_MISC_SEROUT_SPDIF_OE);
327 writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
339 u32 value;
341 value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
342 value |= BIT(BF_DST_CFGX_CAP_ENA);
343 writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
347 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
348 value |= BIT(I2S_OUT_CFGX_CLK_ENA);
349 value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
350 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
352 value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
353 value |= BIT(I2S_IN_STREAM_CFG_CAP_ENA);
354 writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
361 u32 value;
363 value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
364 value &= ~BIT(I2S_IN_STREAM_CFG_CAP_ENA);
365 writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
371 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
372 value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
373 value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
374 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
379 value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
380 value &= ~BIT(BF_DST_CFGX_CAP_ENA);
381 writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
386 u32 value;
391 value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
392 value |= BIT(I2S_OUT_STREAM_ENA);
393 writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
397 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
398 value |= BIT(I2S_OUT_CFGX_CLK_ENA);
399 value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
400 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
402 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
403 value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
404 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
409 value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
410 value |= 0x3;
411 writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
415 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
416 value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
417 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
430 u32 value;
439 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
440 value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
441 value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
442 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
446 value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
447 value |= BIT(aio->portnum);
448 writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
452 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
453 value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
454 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
457 value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
458 value &= ~BIT(aio->portnum);
459 writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
461 value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
462 value &= ~BIT(I2S_OUT_STREAM_ENA);
463 writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
466 value = readl(aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
467 value |= BIT(aio->portnum);
468 writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
469 value &= ~BIT(aio->portnum);
470 writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
473 value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
474 value &= ~0x3;
475 writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
478 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
479 value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
480 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
546 u32 value;
594 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
595 value &= ~(mask << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32);
596 value |= sclk << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32;
597 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
599 "SCLKS_PER_1FS_DIV32 = 0x%x\n", value);
609 value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
610 value &= ~(0xf << I2S_OUT_MCLKRATE_SHIFT);
611 value |= (mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
612 writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
614 dev_dbg(aio->cygaud->dev, "mclk cfg reg = 0x%x\n", value);
626 u32 value;
656 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
657 value &= ~BIT(BF_SRC_CFGX_BUFFER_PAIR_ENABLE);
658 value &= ~BIT(BF_SRC_CFGX_SAMPLE_CH_MODE);
659 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
675 value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
676 value &= ~(mask << BF_SRC_CFGX_BIT_RES);
677 value |= (bitres << BF_SRC_CFGX_BIT_RES);
678 writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
684 value = readl(aio->cygaud->audio +
686 value |= BIT(BF_DST_CFGX_CAP_MODE);
687 writel(value, aio->cygaud->audio +
692 value = readl(aio->cygaud->audio +
694 value &= ~BIT(BF_DST_CFGX_CAP_MODE);
695 writel(value, aio->cygaud->audio +
719 u32 value;
735 value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
736 value &= ~(0xf << I2S_OUT_PLLCLKSEL_SHIFT);
737 value |= (sel << I2S_OUT_PLLCLKSEL_SHIFT);
738 writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
974 u32 value;
992 /* Slot value must be even */
1036 value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
1037 value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
1038 value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
1039 value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
1040 value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
1041 writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
1044 value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
1045 value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
1046 value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
1047 value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
1048 value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
1049 writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
1248 dev_err(&pdev->dev, "Bad value for reg %u\n", rawval);
1276 dev_err(&pdev->dev, "Bad value for port_type %d\n", port_type);