Lines Matching refs:gclk
237 struct clk *gclk;
410 clk_disable_unprepare(dev->gclk);
413 ret = clk_set_min_rate(dev->gclk, params_rate(params) *
417 "unable to set gclk min rate: rate %u * ratio %u + 1\n",
421 ret = clk_prepare_enable(dev->gclk);
423 dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
446 clk_disable_unprepare(dev->gclk);
650 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
680 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
716 ret = clk_prepare_enable(dev->gclk);
734 clk_disable_unprepare(dev->gclk);
773 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
790 rate = clk_get_rate(dev->gclk);
1002 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
1003 if (IS_ERR(dev->gclk)) {
1004 err = PTR_ERR(dev->gclk);
1011 * Signal control need a valid rate on gclk. hw_params() configures
1014 * gclk at a valid rate, here, in initialization, to simplify the
1017 clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1);