Lines Matching refs:dev
231 struct device *dev;
250 struct mchp_i2s_mcc_dev *dev = dev_id;
254 regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
255 regmap_read(dev->regmap, MCHP_I2SMCC_ISRA, &sra);
258 regmap_read(dev->regmap, MCHP_I2SMCC_IMRB, &imrb);
259 regmap_read(dev->regmap, MCHP_I2SMCC_ISRB, &srb);
269 idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
270 MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
274 if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
275 (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
276 (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) {
277 dev->tx_rdy = 1;
278 wake_up_interruptible(&dev->wq_txrdy);
280 if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
281 (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
282 (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) {
283 dev->rx_rdy = 1;
284 wake_up_interruptible(&dev->wq_rxrdy);
286 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
294 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
296 dev_dbg(dev->dev, "%s() clk_id=%d freq=%u dir=%d\n",
303 dev->sysclk = freq;
311 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
313 dev_dbg(dev->dev, "%s() ratio=%u\n", __func__, ratio);
315 dev->frame_length = ratio;
322 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
324 dev_dbg(dev->dev, "%s() fmt=%#x\n", __func__, fmt);
338 dev->fmt = fmt;
348 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
350 dev_dbg(dev->dev,
365 dev->tdm_slots = slots;
366 dev->frame_length = slots * MCHP_I2MCC_TDM_SLOT_WIDTH;
394 static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev,
406 if (!dev->sysclk)
409 sysclk = dev->sysclk;
425 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate,
429 dev_err(dev->dev, "gclk error for rate %lu: %d",
433 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n",
439 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->pclk, clk_rate,
443 dev_err(dev->dev, "pclk error for rate %lu: %d",
447 dev_dbg(dev->dev, "found perfect rate on pclk: %lu\n",
456 dev_err(dev->dev, "unable to change rate to clocks\n");
460 dev_dbg(dev->dev, "source CLK is %s with rate %lu, diff %lu\n",
461 best_clk == dev->pclk ? "pclk" : "gclk",
465 if (dev->sysclk)
469 if (best_clk == dev->gclk)
477 static int mchp_i2s_mcc_is_running(struct mchp_i2s_mcc_dev *dev)
481 regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
490 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
494 unsigned int frame_length = dev->frame_length;
500 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
504 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
506 if (dev->tdm_slots) {
507 dev_err(dev->dev, "I2S with TDM is not supported\n");
513 if (dev->tdm_slots) {
514 dev_err(dev->dev, "Left-Justified with TDM is not supported\n");
523 dev_err(dev->dev, "unsupported bus format\n");
527 switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
531 if (dev->sysclk)
543 if (dev->sysclk)
544 dev_warn(dev->dev, "Unable to generate MCLK in Slave mode\n");
547 dev_err(dev->dev, "unsupported master/slave mode\n");
551 if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
562 dev_err(dev->dev, "unsupported number of audio channels\n");
568 } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {
569 if (dev->tdm_slots) {
570 if (channels % 2 && channels * 2 <= dev->tdm_slots) {
580 channels = dev->tdm_slots;
594 dev->playback.maxburst = 1 << (fls(channels) - 1);
596 dev->capture.maxburst = 1 << (fls(channels) - 1);
624 dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
630 ret = mchp_i2s_mcc_config_divs(dev, bclk_rate, &mra,
633 dev_err(dev->dev,
643 if (mchp_i2s_mcc_is_running(dev)) {
647 regmap_read(dev->regmap, MCHP_I2SMCC_MRA, &mra_cur);
648 regmap_read(dev->regmap, MCHP_I2SMCC_MRB, &mrb_cur);
655 if (mra & MCHP_I2SMCC_MRA_SRCCLK_GCLK && !dev->gclk_use) {
657 ret = clk_set_rate(dev->gclk, rate);
659 dev_err(dev->dev,
665 ret = clk_prepare(dev->gclk);
667 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret);
670 dev->gclk_use = 1;
674 dev->channels = channels;
676 ret = regmap_write(dev->regmap, MCHP_I2SMCC_MRA, mra);
678 if (dev->gclk_use) {
679 clk_unprepare(dev->gclk);
680 dev->gclk_use = 0;
684 return regmap_write(dev->regmap, MCHP_I2SMCC_MRB, mrb);
690 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
695 err = wait_event_interruptible_timeout(dev->wq_txrdy,
696 dev->tx_rdy,
699 dev_warn_once(dev->dev,
701 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
702 MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
703 dev->tx_rdy = 1;
706 err = wait_event_interruptible_timeout(dev->wq_rxrdy,
707 dev->rx_rdy,
710 dev_warn_once(dev->dev,
712 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
713 MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
714 dev->rx_rdy = 1;
718 if (!mchp_i2s_mcc_is_running(dev)) {
719 regmap_write(dev->regmap, MCHP_I2SMCC_CR, MCHP_I2SMCC_CR_CKDIS);
721 if (dev->gclk_running) {
722 clk_disable(dev->gclk);
723 dev->gclk_running = 0;
725 if (dev->gclk_use) {
726 clk_unprepare(dev->gclk);
727 dev->gclk_use = 0;
737 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
756 regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
759 dev->tx_rdy = 0;
764 iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
767 dev->rx_rdy = 0;
772 iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
779 if ((cr & MCHP_I2SMCC_CR_CKEN) && dev->gclk_use &&
780 !dev->gclk_running) {
781 err = clk_enable(dev->gclk);
783 dev_err_once(dev->dev, "failed to enable GCLK: %d\n",
786 dev->gclk_running = 1;
790 regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
791 regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);
799 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
802 if (!mchp_i2s_mcc_is_running(dev)) {
803 return regmap_write(dev->regmap, MCHP_I2SMCC_CR,
823 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
825 init_waitqueue_head(&dev->wq_txrdy);
826 init_waitqueue_head(&dev->wq_rxrdy);
827 dev->tx_rdy = 1;
828 dev->rx_rdy = 1;
830 snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
883 struct mchp_i2s_mcc_dev *dev;
891 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
892 if (!dev)
896 base = devm_ioremap_resource(&pdev->dev, mem);
900 regmap = devm_regmap_init_mmio(&pdev->dev, base,
909 err = devm_request_irq(&pdev->dev, irq, mchp_i2s_mcc_interrupt, 0,
910 dev_name(&pdev->dev), dev);
914 dev->pclk = devm_clk_get(&pdev->dev, "pclk");
915 if (IS_ERR(dev->pclk)) {
916 err = PTR_ERR(dev->pclk);
917 dev_err(&pdev->dev,
923 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
924 if (IS_ERR(dev->gclk)) {
925 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
927 dev_warn(&pdev->dev,
929 dev->gclk = NULL;
932 dev->dev = &pdev->dev;
933 dev->regmap = regmap;
934 platform_set_drvdata(pdev, dev);
936 err = clk_prepare_enable(dev->pclk);
938 dev_err(&pdev->dev,
943 err = devm_snd_soc_register_component(&pdev->dev,
947 dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
948 clk_disable_unprepare(dev->pclk);
952 dev->playback.addr = (dma_addr_t)mem->start + MCHP_I2SMCC_THR;
953 dev->capture.addr = (dma_addr_t)mem->start + MCHP_I2SMCC_RHR;
955 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
957 dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
958 clk_disable_unprepare(dev->pclk);
963 regmap_read(dev->regmap, MCHP_I2SMCC_VERSION, &version);
964 dev_info(&pdev->dev, "hw version: %#lx\n",
972 struct mchp_i2s_mcc_dev *dev = platform_get_drvdata(pdev);
974 clk_disable_unprepare(dev->pclk);