Lines Matching refs:acp_mmio
118 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
120 return readl(acp_mmio + (reg * 4));
123 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
125 writel(val, acp_mmio + (reg * 4));
132 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
139 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
141 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
146 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
153 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
156 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
160 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
169 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
170 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
172 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
173 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
176 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
177 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
180 static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)
186 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
188 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
190 ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),
202 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
247 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
250 pre_config_reset(acp_mmio, ch);
251 config_acp_dma_channel(acp_mmio, ch,
261 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
287 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
290 pre_config_reset(acp_mmio, ch);
292 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
298 static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,
310 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
315 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
319 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
323 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
330 static void config_acp_dma(void __iomem *acp_mmio,
336 acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages,
347 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
352 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
358 static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
376 val = acp_reg_read(acp_mmio,
379 acp_reg_write(0x0, acp_mmio, ch_reg);
381 acp_reg_write(0x2, acp_mmio, res_reg);
383 val = acp_reg_read(acp_mmio, imr_reg);
386 acp_reg_write(val, acp_mmio, imr_reg);
387 acp_reg_write(0x1, acp_mmio, ch_reg);
390 static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
406 val = acp_reg_read(acp_mmio, imr_reg);
409 acp_reg_write(val, acp_mmio, imr_reg);
410 acp_reg_write(0x0, acp_mmio, ch_reg);
414 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)
419 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
422 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
449 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
453 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
459 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
468 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
469 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
477 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
482 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
490 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
503 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
521 val = acp_reg_read(acp_mmio, req_reg);
539 acp_reg_write(val, acp_mmio, req_reg);
541 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
551 static int acp_init(void __iomem *acp_mmio, u32 asic_type)
557 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
560 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
564 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
576 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
578 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
583 val = acp_reg_read(acp_mmio, mmACP_STATUS);
594 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
596 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
600 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
602 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
606 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
610 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
617 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
618 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
621 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
625 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
627 acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
639 acp_set_sram_bank_state(acp_mmio, bank, false);
645 static int acp_deinit(void __iomem *acp_mmio)
651 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
654 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
658 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
669 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
671 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
676 val = acp_reg_read(acp_mmio, mmACP_STATUS);
694 void __iomem *acp_mmio;
699 acp_mmio = irq_data->acp_mmio;
701 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
710 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
718 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
723 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==
728 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
730 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
734 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
739 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==
744 config_acp_dma_channel(acp_mmio,
747 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
753 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
800 adata->acp_mmio = intr_data->acp_mmio;
811 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
821 acp_set_sram_bank_state(intr_data->acp_mmio,
827 acp_set_sram_bank_state(intr_data->acp_mmio,
863 val = acp_reg_read(adata->acp_mmio,
884 acp_reg_write(val, adata->acp_mmio,
970 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
980 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
988 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
990 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio,
1018 dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr);
1062 config_acp_dma_channel(rtd->acp_mmio,
1066 config_acp_dma_channel(rtd->acp_mmio,
1090 acp_dma_cap_channel_disable(rtd->acp_mmio,
1092 acp_dma_cap_channel_enable(rtd->acp_mmio,
1096 acp_dma_cap_channel_disable(rtd->acp_mmio,
1098 acp_dma_cap_channel_enable(rtd->acp_mmio,
1101 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1103 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1104 acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
1111 acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1112 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1170 acp_set_sram_bank_state(adata->acp_mmio,
1184 acp_set_sram_bank_state(adata->acp_mmio,
1196 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1230 audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0);
1231 if (IS_ERR(audio_drv_data->acp_mmio))
1232 return PTR_ERR(audio_drv_data->acp_mmio);
1263 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
1288 status = acp_deinit(adata->acp_mmio);
1303 status = acp_init(adata->acp_mmio, adata->asic_type);
1317 acp_set_sram_bank_state(adata->acp_mmio, bank,
1321 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1327 acp_set_sram_bank_state(adata->acp_mmio, bank,
1331 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1337 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1342 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1345 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1354 status = acp_deinit(adata->acp_mmio);
1357 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1366 status = acp_init(adata->acp_mmio, adata->asic_type);
1371 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);