Lines Matching defs:wcreg
219 u32 wcreg; /* cached write control register value */
261 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
262 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
540 writel(rme96->wcreg | RME96_WCR_PD,
542 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
548 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
549 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
557 rme96->wcreg |= RME96_WCR_MONITOR_0;
559 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
562 rme96->wcreg |= RME96_WCR_MONITOR_1;
564 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
566 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
573 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
574 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
583 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
587 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
591 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
595 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
601 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
673 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
680 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
681 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
695 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
704 ds = rme96->wcreg & RME96_WCR_DS;
707 rme96->wcreg &= ~RME96_WCR_DS;
708 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
712 rme96->wcreg &= ~RME96_WCR_DS;
713 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
717 rme96->wcreg &= ~RME96_WCR_DS;
718 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
722 rme96->wcreg |= RME96_WCR_DS;
723 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
727 rme96->wcreg |= RME96_WCR_DS;
728 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
732 rme96->wcreg |= RME96_WCR_DS;
733 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
739 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
740 (ds && !(rme96->wcreg & RME96_WCR_DS)))
746 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
800 rme96->wcreg &= ~RME96_WCR_MASTER;
805 rme96->wcreg |= RME96_WCR_MASTER;
810 rme96->wcreg |= RME96_WCR_MASTER;
816 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
827 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
839 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
843 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
847 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
859 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
888 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
898 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
899 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
916 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
919 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
929 rme96->wcreg &= ~RME96_WCR_MODE24;
932 rme96->wcreg |= RME96_WCR_MODE24;
937 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
946 rme96->wcreg &= ~RME96_WCR_MODE24_2;
949 rme96->wcreg |= RME96_WCR_MODE24_2;
954 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
964 rme96->wcreg &= ~RME96_WCR_ISEL;
967 rme96->wcreg |= RME96_WCR_ISEL;
973 rme96->wcreg &= ~RME96_WCR_IDIS;
974 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
992 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1024 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1025 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1026 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1113 rme96->wcreg |= RME96_WCR_START;
1115 rme96->wcreg &= ~RME96_WCR_START;
1117 rme96->wcreg |= RME96_WCR_START_2;
1119 rme96->wcreg &= ~RME96_WCR_START_2;
1120 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1192 rme96->wcreg &= ~RME96_WCR_ADAT;
1193 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1198 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1261 rme96->wcreg |= RME96_WCR_ADAT;
1262 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1267 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1327 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1677 rme96->wcreg =
1685 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1735 if (rme96->wcreg & RME96_WCR_IDIS) {
1738 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1772 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1779 if (rme96->wcreg & RME96_WCR_SEL) {
1786 if (rme96->wcreg & RME96_WCR_MODE24) {
1793 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1802 if (rme96->wcreg & RME96_WCR_PRO) {
1807 if (rme96->wcreg & RME96_WCR_EMP) {
1812 if (rme96->wcreg & RME96_WCR_DOLBY) {
1869 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1882 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1883 change = val != rme96->wcreg;
1884 rme96->wcreg = val;
2182 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2183 rme96->wcreg |= val;
2184 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);