Lines Matching refs:rmh
43 struct pcxhr_rmh rmh;
45 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
47 rmh.cmd[0] |= IO_NUM_REG_IN_ANA_LEVEL;
48 rmh.cmd[2] = chip->analog_capture_volume[channel];
50 rmh.cmd[0] |= IO_NUM_REG_OUT_ANA_LEVEL;
56 rmh.cmd[2] = PCXHR_LINE_PLAYBACK_LEVEL_MAX - vol;
58 rmh.cmd[1] = 1 << ((2 * chip->chip_idx) + channel); /* audio mask */
59 rmh.cmd_len = 3;
60 err = pcxhr_send_msg(chip->mgr, &rmh);
249 struct pcxhr_rmh rmh;
262 pcxhr_init_rmh(&rmh, CMD_STREAM_OUT_LEVEL_ADJUST);
264 pcxhr_set_pipe_cmd_params(&rmh, 0, pipe->first_audio, 0, 1<<idx);
266 rmh.cmd[0] |= MORE_THAN_ONE_STREAM_LEVEL;
267 rmh.cmd[2] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_1_MASK;
268 rmh.cmd[2] |= (left << 10);
269 rmh.cmd[3] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_2_MASK;
270 rmh.cmd[3] |= right;
271 rmh.cmd_len = 4;
273 err = pcxhr_send_msg(chip->mgr, &rmh);
293 struct pcxhr_rmh rmh;
301 pcxhr_init_rmh(&rmh, CMD_AUDIO_LEVEL_ADJUST);
303 pcxhr_set_pipe_cmd_params(&rmh, capture, 0, 0,
308 rmh.cmd[0] |= VALID_AUDIO_IO_DIGITAL_LEVEL;
311 rmh.cmd[2] = chip->digital_capture_volume[channel];
313 rmh.cmd[0] |= VALID_AUDIO_IO_MONITOR_LEVEL |
318 rmh.cmd[2] = chip->monitoring_volume[channel] << 10;
320 rmh.cmd[2] |= AUDIO_IO_HAS_MUTE_MONITOR_1;
322 rmh.cmd_len = 3;
324 err = pcxhr_send_msg(chip->mgr, &rmh);
573 struct pcxhr_rmh rmh;
594 pcxhr_init_rmh(&rmh, CMD_RESYNC_AUDIO_INPUTS);
595 rmh.cmd[0] |= (1 << chip->chip_idx);
596 err = pcxhr_send_msg(chip->mgr, &rmh);
609 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
610 rmh.cmd_len = 2;
611 rmh.cmd[0] |= IO_NUM_REG_CONFIG_SRC;
612 rmh.cmd[1] = src_config;
613 err = pcxhr_send_msg(chip->mgr, &rmh);
619 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
620 rmh.cmd_len = 3;
621 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
622 rmh.cmd[1] = codec;
623 rmh.cmd[2] = ((CS8420_DATA_FLOW_CTL & CHIP_SIG_AND_MAP_SPI) |
625 err = pcxhr_send_msg(chip->mgr, &rmh);
628 rmh.cmd[2] = ((CS8420_CLOCK_SRC_CTL & CHIP_SIG_AND_MAP_SPI) |
630 err = pcxhr_send_msg(chip->mgr, &rmh);
856 struct pcxhr_rmh rmh;
858 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
859 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
862 case 0: rmh.cmd[1] = CS8420_01_CS; break;
863 case 1: rmh.cmd[1] = CS8420_23_CS; break;
864 case 2: rmh.cmd[1] = CS8420_45_CS; break;
865 case 3: rmh.cmd[1] = CS8420_67_CS; break;
870 case 0: rmh.cmd[2] = CS8416_CSB0; break;
871 case 1: rmh.cmd[2] = CS8416_CSB1; break;
872 case 2: rmh.cmd[2] = CS8416_CSB2; break;
873 case 3: rmh.cmd[2] = CS8416_CSB3; break;
874 case 4: rmh.cmd[2] = CS8416_CSB4; break;
880 case 0: rmh.cmd[2] = CS8420_CSB0; break;
881 case 1: rmh.cmd[2] = CS8420_CSB1; break;
882 case 2: rmh.cmd[2] = CS8420_CSB2; break;
883 case 3: rmh.cmd[2] = CS8420_CSB3; break;
884 case 4: rmh.cmd[2] = CS8420_CSB4; break;
889 rmh.cmd[1] &= 0x0fffff;
891 rmh.cmd[2] &= CHIP_SIG_AND_MAP_SPI;
892 rmh.cmd_len = 3;
893 err = pcxhr_send_msg(chip->mgr, &rmh);
898 temp = (unsigned char)rmh.stat[1];
904 if (rmh.stat[1] & (1 << i))
956 struct pcxhr_rmh rmh;
966 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
967 rmh.cmd[0] |= IO_NUM_REG_CUER;
968 rmh.cmd[1] = cmd;
969 rmh.cmd_len = 2;
973 err = pcxhr_send_msg(chip->mgr, &rmh);