Lines Matching defs:ctl
197 strlcpy(elem_id.name, spec->wm8776.ctl[WM8776_CTL_HP_SW].name,
308 struct snd_kcontrol *ctl;
312 spec->wm8776.ctl[WM8776_CTL_DAC_VOL].name = front_volume;
313 spec->wm8776.ctl[WM8776_CTL_DAC_SW].name = front_switch;
314 spec->wm8776.ctl[WM8776_CTL_DAC_ZC_SW].name = front_zc;
315 spec->wm8776.ctl[WM8776_CTL_AUX_SW].name = NULL;
316 spec->wm8776.ctl[WM8776_CTL_DAC_IZD_SW].name = front_izd;
317 spec->wm8776.ctl[WM8776_CTL_PHASE_SW].name = front_phase;
318 spec->wm8776.ctl[WM8776_CTL_DEEMPH_SW].name = front_deemph;
319 spec->wm8776.ctl[WM8776_CTL_INPUT1_SW].name = ain1_switch;
320 spec->wm8776.ctl[WM8776_CTL_INPUT2_SW].name = ain2_switch;
321 spec->wm8776.ctl[WM8776_CTL_INPUT3_SW].name = ain3_switch;
322 spec->wm8776.ctl[WM8776_CTL_INPUT4_SW].name = ain4_switch;
323 spec->wm8776.ctl[WM8776_CTL_INPUT5_SW].name = ain5_switch;
325 spec->wm8766.ctl[WM8766_CTL_CH1_VOL].name = rear_volume;
326 spec->wm8766.ctl[WM8766_CTL_CH2_VOL].name = clfe_volume;
327 spec->wm8766.ctl[WM8766_CTL_CH3_VOL].name = NULL;
328 spec->wm8766.ctl[WM8766_CTL_CH1_SW].name = rear_switch;
329 spec->wm8766.ctl[WM8766_CTL_CH2_SW].name = clfe_switch;
330 spec->wm8766.ctl[WM8766_CTL_CH3_SW].name = NULL;
331 spec->wm8766.ctl[WM8766_CTL_PHASE1_SW].name = rear_phase;
332 spec->wm8766.ctl[WM8766_CTL_PHASE2_SW].name = clfe_phase;
333 spec->wm8766.ctl[WM8766_CTL_PHASE3_SW].name = NULL;
334 spec->wm8766.ctl[WM8766_CTL_DEEMPH1_SW].name = rear_deemph;
335 spec->wm8766.ctl[WM8766_CTL_DEEMPH2_SW].name = clfe_deemph;
336 spec->wm8766.ctl[WM8766_CTL_DEEMPH3_SW].name = NULL;
337 spec->wm8766.ctl[WM8766_CTL_IZD_SW].name = rear_clfe_izd;
338 spec->wm8766.ctl[WM8766_CTL_ZC_SW].name = rear_clfe_zc;
350 ctl = snd_ctl_new1(&cont, ice);
351 if (!ctl)
353 err = snd_ctl_add(ice->card, ctl);