Lines Matching defs:control_reg
117 u32 control_reg;
150 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
151 err = write_control_reg(chip, control_reg, true);
198 u32 control_reg, clock;
244 control_reg = le32_to_cpu(chip->comm_page->control_register);
245 control_reg &= GML_CLOCK_CLEAR_MASK;
246 control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
261 if (control_reg & GML_SPDIF_PRO_MODE)
286 control_reg |= clock;
293 return write_control_reg(chip, control_reg, force_write);
300 u32 control_reg, clocks_from_dsp;
304 control_reg = le32_to_cpu(chip->comm_page->control_register) &
321 control_reg |= GML_SPDIF_CLOCK;
323 control_reg |= GML_DOUBLE_SPEED_MODE;
325 control_reg &= ~GML_DOUBLE_SPEED_MODE;
334 control_reg |= GML_WORD_CLOCK;
336 control_reg |= GML_DOUBLE_SPEED_MODE;
338 control_reg &= ~GML_DOUBLE_SPEED_MODE;
344 control_reg |= GML_ADAT_CLOCK;
345 control_reg &= ~GML_DOUBLE_SPEED_MODE;
354 return write_control_reg(chip, control_reg, true);
361 u32 control_reg;
390 control_reg = le32_to_cpu(chip->comm_page->control_register);
391 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
396 control_reg |= GML_SPDIF_OPTICAL_MODE;
408 control_reg |= GML_ADAT_MODE;
409 control_reg &= ~GML_DOUBLE_SPEED_MODE;
413 err = write_control_reg(chip, control_reg, false);