Lines Matching defs:control_reg
159 u32 control_reg, clock, base_rate;
176 control_reg = le32_to_cpu(chip->comm_page->control_register);
177 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
194 if (control_reg & GML_SPDIF_PRO_MODE)
219 control_reg |= GML_DOUBLE_SPEED_MODE;
237 control_reg |= clock;
242 "set_sample_rate: %d clock %d\n", rate, control_reg);
244 return write_control_reg(chip, control_reg, false);
251 u32 control_reg, clocks_from_dsp;
254 control_reg = le32_to_cpu(chip->comm_page->control_register) &
266 control_reg |= GML_SPDIF_CLOCK;
268 control_reg &= ~GML_DOUBLE_SPEED_MODE;
271 control_reg |= GML_WORD_CLOCK;
273 control_reg |= GML_DOUBLE_SPEED_MODE;
275 control_reg &= ~GML_DOUBLE_SPEED_MODE;
280 control_reg |= GML_ADAT_CLOCK;
281 control_reg &= ~GML_DOUBLE_SPEED_MODE;
290 return write_control_reg(chip, control_reg, true);
332 u32 control_reg;
370 control_reg = le32_to_cpu(chip->comm_page->control_register);
371 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
375 control_reg |= GML_SPDIF_OPTICAL_MODE;
381 control_reg |= GML_ADAT_MODE;
382 control_reg &= ~GML_DOUBLE_SPEED_MODE;
386 err = write_control_reg(chip, control_reg, true);