Lines Matching defs:clock
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
91 /* Map the DSP clock detect bits to the generic driver clock detect bits */
147 48 kHz, internal clock, S/PDIF RCA mode */
159 u32 control_reg, clock, base_rate;
165 /* Only set the clock for internal mode. */
168 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
179 clock = 0;
183 clock = GML_96KHZ;
186 clock = GML_88KHZ;
189 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
192 clock = GML_44KHZ;
195 clock |= GML_SPDIF_SAMPLE_RATE0;
198 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
202 clock = GML_22KHZ;
205 clock = GML_16KHZ;
208 clock = GML_11KHZ;
211 clock = GML_8KHZ;
216 clock = LAYLA24_CONTINUOUS_CLOCK;
237 control_reg |= clock;
242 "set_sample_rate: %d clock %d\n", rate, control_reg);
249 static int set_input_clock(struct echoaudio *chip, u16 clock)
253 /* Mask off the clock select bits */
258 /* Pick the new clock */
259 switch (clock) {
285 "Input clock 0x%x not supported for Layla24\n", clock);
289 chip->input_clock = clock;
336 /* Set clock to "internal" if it's not compatible with the new mode */