Lines Matching defs:control_reg
124 u32 control_reg;
154 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
155 err = write_control_reg(chip, control_reg, true);
164 u32 control_reg, clock;
182 control_reg = le32_to_cpu(chip->comm_page->control_register);
183 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
198 if (control_reg & GML_SPDIF_PRO_MODE)
223 control_reg |= clock;
229 return write_control_reg(chip, control_reg, false);
236 u32 control_reg, clocks_from_dsp;
240 control_reg = le32_to_cpu(chip->comm_page->control_register) &
251 control_reg |= GML_SPDIF_CLOCK;
253 control_reg |= GML_DOUBLE_SPEED_MODE;
255 control_reg &= ~GML_DOUBLE_SPEED_MODE;
260 control_reg |= GML_ADAT_CLOCK;
261 control_reg &= ~GML_DOUBLE_SPEED_MODE;
264 control_reg |= GML_ESYNC_CLOCK;
265 control_reg &= ~GML_DOUBLE_SPEED_MODE;
268 control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;
277 return write_control_reg(chip, control_reg, true);
284 u32 control_reg;
314 control_reg = le32_to_cpu(chip->comm_page->control_register);
315 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
320 control_reg |= GML_SPDIF_OPTICAL_MODE;
325 control_reg |= GML_SPDIF_CDROM_MODE;
331 control_reg |= GML_ADAT_MODE;
332 control_reg &= ~GML_DOUBLE_SPEED_MODE;
336 err = write_control_reg(chip, control_reg, true);