Lines Matching defs:control_reg
145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
147 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
151 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
155 control_reg |= E3G_SPDIF_SAMPLE_RATE0;
158 control_reg |= E3G_SPDIF_SAMPLE_RATE1;
163 control_reg |= E3G_SPDIF_PRO_MODE;
166 control_reg |= E3G_SPDIF_NOT_AUDIO;
168 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
171 return control_reg;
179 u32 control_reg;
181 control_reg = le32_to_cpu(chip->comm_page->control_register);
183 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
184 return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
260 u32 control_reg, clock, base_rate, frq_reg;
278 control_reg = le32_to_cpu(chip->comm_page->control_register);
279 control_reg &= E3G_CLOCK_CLEAR_MASK;
304 control_reg |= clock;
305 control_reg = set_spdif_bits(chip, control_reg, rate);
320 "SetSampleRate: %d clock %x\n", rate, control_reg);
323 return write_control_reg(chip, control_reg, frq_reg, 0);
331 u32 control_reg, clocks_from_dsp;
335 control_reg = le32_to_cpu(chip->comm_page->control_register) &
346 control_reg |= E3G_SPDIF_CLOCK;
348 control_reg |= E3G_DOUBLE_SPEED_MODE;
350 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
355 control_reg |= E3G_ADAT_CLOCK;
356 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
359 control_reg |= E3G_WORD_CLOCK;
361 control_reg |= E3G_DOUBLE_SPEED_MODE;
363 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
372 return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
379 u32 control_reg;
408 control_reg = le32_to_cpu(chip->comm_page->control_register);
409 control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
414 control_reg |= E3G_SPDIF_OPTICAL_MODE;
420 control_reg |= E3G_ADAT_MODE;
421 control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */
425 err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);