Lines Matching refs:chip
61 #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
62 #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
499 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
502 writel(val, chip->ba0 + offset);
505 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
507 return readl(chip->ba0 + offset);
520 struct cs4281 *chip = ac97->private_data;
535 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
536 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
537 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
548 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
552 dev_err(chip->card->dev,
559 struct cs4281 *chip = ac97->private_data;
575 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
590 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
591 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
592 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
609 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
613 dev_err(chip->card->dev,
628 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
633 dev_err(chip->card->dev,
643 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
656 struct cs4281 *chip = snd_pcm_substream_chip(substream);
658 spin_lock(&chip->reg_lock);
670 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
685 spin_unlock(&chip->reg_lock);
688 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
689 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
690 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
691 spin_unlock(&chip->reg_lock);
718 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
744 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
745 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
746 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
747 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
748 (chip->src_right_play_slot << 8) |
749 (chip->src_left_rec_slot << 16) |
750 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
754 if (dma->left_slot == chip->src_left_play_slot) {
756 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
757 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
760 if (dma->left_slot == chip->src_left_rec_slot) {
762 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
763 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
769 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
775 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
778 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
780 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
787 struct cs4281 *chip = snd_pcm_substream_chip(substream);
789 spin_lock_irq(&chip->reg_lock);
790 snd_cs4281_mode(chip, dma, runtime, 0, 1);
791 spin_unlock_irq(&chip->reg_lock);
799 struct cs4281 *chip = snd_pcm_substream_chip(substream);
801 spin_lock_irq(&chip->reg_lock);
802 snd_cs4281_mode(chip, dma, runtime, 1, 1);
803 spin_unlock_irq(&chip->reg_lock);
811 struct cs4281 *chip = snd_pcm_substream_chip(substream);
814 dev_dbg(chip->card->dev,
816 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
820 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
875 struct cs4281 *chip = snd_pcm_substream_chip(substream);
879 dma = &chip->dma[0];
894 struct cs4281 *chip = snd_pcm_substream_chip(substream);
898 dma = &chip->dma[1];
943 static int snd_cs4281_pcm(struct cs4281 *chip, int device)
948 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
955 pcm->private_data = chip;
958 chip->pcm = pcm;
960 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
985 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
990 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
991 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1001 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1007 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1008 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1012 snd_cs4281_pokeBA0(chip, regL, volL);
1017 snd_cs4281_pokeBA0(chip, regR, volR);
1049 struct cs4281 *chip = bus->private_data;
1050 chip->ac97_bus = NULL;
1055 struct cs4281 *chip = ac97->private_data;
1057 chip->ac97_secondary = NULL;
1059 chip->ac97 = NULL;
1062 static int snd_cs4281_mixer(struct cs4281 *chip)
1064 struct snd_card *card = chip->card;
1072 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1074 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1077 ac97.private_data = chip;
1079 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1081 if (chip->dual_codec) {
1083 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1086 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1088 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1101 struct cs4281 *chip = entry->private_data;
1104 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1105 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1113 struct cs4281 *chip = entry->private_data;
1115 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1125 struct cs4281 *chip = entry->private_data;
1127 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1140 static void snd_cs4281_proc_init(struct cs4281 *chip)
1144 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1145 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1147 entry->private_data = chip;
1151 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1153 entry->private_data = chip;
1167 struct cs4281 *chip = gameport_get_port_data(gameport);
1169 if (snd_BUG_ON(!chip))
1171 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1176 struct cs4281 *chip = gameport_get_port_data(gameport);
1178 if (snd_BUG_ON(!chip))
1180 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1187 struct cs4281 *chip = gameport_get_port_data(gameport);
1190 if (snd_BUG_ON(!chip))
1193 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1194 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1195 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1227 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1231 chip->gameport = gp = gameport_allocate_port();
1233 dev_err(chip->card->dev,
1239 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1240 gameport_set_dev_parent(gp, &chip->pci->dev);
1245 gameport_set_port_data(gp, chip);
1247 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1248 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1255 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1257 if (chip->gameport) {
1258 gameport_unregister_port(chip->gameport);
1259 chip->gameport = NULL;
1263 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1264 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1267 static int snd_cs4281_free(struct cs4281 *chip)
1269 snd_cs4281_free_gameport(chip);
1272 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1274 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1276 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1278 pci_set_power_state(chip->pci, PCI_D3hot);
1280 if (chip->irq >= 0)
1281 free_irq(chip->irq, chip);
1282 iounmap(chip->ba0);
1283 iounmap(chip->ba1);
1284 pci_release_regions(chip->pci);
1285 pci_disable_device(chip->pci);
1287 kfree(chip);
1293 struct cs4281 *chip = device->device_data;
1294 return snd_cs4281_free(chip);
1297 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1304 struct cs4281 *chip;
1314 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1315 if (chip == NULL) {
1319 spin_lock_init(&chip->reg_lock);
1320 chip->card = card;
1321 chip->pci = pci;
1322 chip->irq = -1;
1328 chip->dual_codec = dual_codec;
1331 kfree(chip);
1335 chip->ba0_addr = pci_resource_start(pci, 0);
1336 chip->ba1_addr = pci_resource_start(pci, 1);
1338 chip->ba0 = pci_ioremap_bar(pci, 0);
1339 chip->ba1 = pci_ioremap_bar(pci, 1);
1340 if (!chip->ba0 || !chip->ba1) {
1341 snd_cs4281_free(chip);
1346 KBUILD_MODNAME, chip)) {
1348 snd_cs4281_free(chip);
1351 chip->irq = pci->irq;
1352 card->sync_irq = chip->irq;
1354 tmp = snd_cs4281_chip_init(chip);
1356 snd_cs4281_free(chip);
1360 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1361 snd_cs4281_free(chip);
1365 snd_cs4281_proc_init(chip);
1367 *rchip = chip;
1371 static int snd_cs4281_chip_init(struct cs4281 *chip)
1377 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1378 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1380 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1383 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1385 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1386 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1388 dev_err(chip->card->dev,
1397 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1399 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1400 dev_err(chip->card->dev,
1404 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1405 dev_err(chip->card->dev,
1411 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1420 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1421 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1425 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1432 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1434 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1437 if (chip->dual_codec)
1438 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1443 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1444 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1450 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1452 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1463 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1468 dev_err(chip->card->dev, "DLLRDY not seen\n");
1478 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1489 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1494 dev_err(chip->card->dev,
1496 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1500 if (chip->dual_codec) {
1503 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1507 dev_info(chip->card->dev,
1509 chip->dual_codec = 0;
1518 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1531 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1538 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1547 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1553 struct cs4281_dma *dma = &chip->dma[tmp];
1564 snd_cs4281_pokeBA0(chip, dma->regFCR,
1571 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1572 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1573 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1574 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1577 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1580 BA0_FCR_OF(chip->dma[0].fifo_offset);
1581 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1582 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1583 (chip->src_right_play_slot << 8) |
1584 (chip->src_left_rec_slot << 16) |
1585 (chip->src_right_rec_slot << 24));
1588 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1589 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1592 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1594 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1609 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1611 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1613 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1618 struct cs4281 *chip = substream->rmidi->private_data;
1620 spin_lock_irq(&chip->reg_lock);
1621 chip->midcr |= BA0_MIDCR_RXE;
1622 chip->midi_input = substream;
1623 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1624 snd_cs4281_midi_reset(chip);
1626 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1628 spin_unlock_irq(&chip->reg_lock);
1634 struct cs4281 *chip = substream->rmidi->private_data;
1636 spin_lock_irq(&chip->reg_lock);
1637 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1638 chip->midi_input = NULL;
1639 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1640 snd_cs4281_midi_reset(chip);
1642 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1644 chip->uartm &= ~CS4281_MODE_INPUT;
1645 spin_unlock_irq(&chip->reg_lock);
1651 struct cs4281 *chip = substream->rmidi->private_data;
1653 spin_lock_irq(&chip->reg_lock);
1654 chip->uartm |= CS4281_MODE_OUTPUT;
1655 chip->midcr |= BA0_MIDCR_TXE;
1656 chip->midi_output = substream;
1657 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1658 snd_cs4281_midi_reset(chip);
1660 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1662 spin_unlock_irq(&chip->reg_lock);
1668 struct cs4281 *chip = substream->rmidi->private_data;
1670 spin_lock_irq(&chip->reg_lock);
1671 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1672 chip->midi_output = NULL;
1673 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1674 snd_cs4281_midi_reset(chip);
1676 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1678 chip->uartm &= ~CS4281_MODE_OUTPUT;
1679 spin_unlock_irq(&chip->reg_lock);
1686 struct cs4281 *chip = substream->rmidi->private_data;
1688 spin_lock_irqsave(&chip->reg_lock, flags);
1690 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1691 chip->midcr |= BA0_MIDCR_RIE;
1692 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1695 if (chip->midcr & BA0_MIDCR_RIE) {
1696 chip->midcr &= ~BA0_MIDCR_RIE;
1697 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1700 spin_unlock_irqrestore(&chip->reg_lock, flags);
1706 struct cs4281 *chip = substream->rmidi->private_data;
1709 spin_lock_irqsave(&chip->reg_lock, flags);
1711 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1712 chip->midcr |= BA0_MIDCR_TIE;
1714 while ((chip->midcr & BA0_MIDCR_TIE) &&
1715 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1717 chip->midcr &= ~BA0_MIDCR_TIE;
1719 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1722 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1725 if (chip->midcr & BA0_MIDCR_TIE) {
1726 chip->midcr &= ~BA0_MIDCR_TIE;
1727 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1730 spin_unlock_irqrestore(&chip->reg_lock, flags);
1747 static int snd_cs4281_midi(struct cs4281 *chip, int device)
1752 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1758 rmidi->private_data = chip;
1759 chip->rmidi = rmidi;
1769 struct cs4281 *chip = dev_id;
1773 if (chip == NULL)
1775 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1777 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1784 cdma = &chip->dma[dma];
1785 spin_lock(&chip->reg_lock);
1787 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1793 chip->spurious_dhtc_irq++;
1794 spin_unlock(&chip->reg_lock);
1799 chip->spurious_dtc_irq++;
1800 spin_unlock(&chip->reg_lock);
1803 spin_unlock(&chip->reg_lock);
1808 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1811 spin_lock(&chip->reg_lock);
1812 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1813 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1814 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1816 snd_rawmidi_receive(chip->midi_input, &c, 1);
1818 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1819 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1821 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1822 chip->midcr &= ~BA0_MIDCR_TIE;
1823 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1826 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1828 spin_unlock(&chip->reg_lock);
1832 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1845 struct cs4281 *chip = opl3->private_data;
1849 port = chip->ba0 + BA0_B1AP; /* right port */
1851 port = chip->ba0 + BA0_B0AP; /* left port */
1869 struct cs4281 *chip;
1885 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1889 card->private_data = chip;
1891 if ((err = snd_cs4281_mixer(chip)) < 0) {
1895 if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
1899 if ((err = snd_cs4281_midi(chip, 0)) < 0) {
1907 opl3->private_data = chip;
1914 snd_cs4281_create_gameport(chip);
1919 chip->ba0_addr,
1920 chip->irq);
1963 struct cs4281 *chip = card->private_data;
1968 snd_ac97_suspend(chip->ac97);
1969 snd_ac97_suspend(chip->ac97_secondary);
1971 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1973 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1976 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1981 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
1984 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1987 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1990 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1993 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1995 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1997 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2004 struct cs4281 *chip = card->private_data;
2008 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2010 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2012 snd_cs4281_chip_init(chip);
2017 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2019 snd_ac97_resume(chip->ac97);
2020 snd_ac97_resume(chip->ac97_secondary);
2022 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2024 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);