Lines Matching refs:BA0_CLKCR1
206 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
1274 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1420 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1450 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1452 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1463 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1971 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1973 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1990 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1995 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1997 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2008 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2010 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2022 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2024 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);