Lines Matching defs:tmp
1305 unsigned int tmp;
1354 tmp = snd_cs4281_chip_init(chip);
1355 if (tmp) {
1357 return tmp;
1373 unsigned int tmp;
1378 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1379 if (tmp & BA0_EPPMC_FPDN)
1380 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1383 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1384 if (tmp != BA0_CFLR_DEFAULT) {
1386 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1387 if (tmp != BA0_CFLR_DEFAULT) {
1389 "CFLR setup failed (0x%x)\n", tmp);
1399 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1401 "SERC1 AC'97 check failed (0x%x)\n", tmp);
1404 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1406 "SERC2 AC'97 check failed (0x%x)\n", tmp);
1552 for (tmp = 0; tmp < 4; tmp++) {
1553 struct cs4281_dma *dma = &chip->dma[tmp];
1554 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1555 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1556 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1557 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1558 dma->regDMR = BA0_DMR0 + (tmp * 8);
1559 dma->regDCR = BA0_DCR0 + (tmp * 8);
1560 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1561 dma->regFCR = BA0_FCR0 + (tmp * 4);
1562 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1563 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;