Lines Matching defs:dma
458 struct cs4281_dma dma[4];
655 struct cs4281_dma *dma = substream->runtime->private_data;
661 dma->valDCR |= BA0_DCR_MSK;
662 dma->valFCR |= BA0_FCR_FEN;
665 dma->valDCR &= ~BA0_DCR_MSK;
666 dma->valFCR &= ~BA0_FCR_FEN;
670 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
671 dma->valDMR |= BA0_DMR_DMA;
672 dma->valDCR &= ~BA0_DCR_MSK;
673 dma->valFCR |= BA0_FCR_FEN;
677 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
678 dma->valDCR |= BA0_DCR_MSK;
679 dma->valFCR &= ~BA0_FCR_FEN;
681 if (dma->regFCR != BA0_FCR0)
682 dma->valFCR &= ~BA0_FCR_FEN;
688 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
689 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
690 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
718 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
724 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
727 dma->valDMR |= BA0_DMR_MONO;
729 dma->valDMR |= BA0_DMR_USIGN;
731 dma->valDMR |= BA0_DMR_BEND;
733 case 8: dma->valDMR |= BA0_DMR_SIZE8;
735 dma->valDMR |= BA0_DMR_SWAPC;
737 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
739 dma->frag = 0; /* for workaround */
740 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
742 dma->valDCR |= BA0_DCR_HTCIE;
744 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
745 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
746 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
754 if (dma->left_slot == chip->src_left_play_slot) {
756 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
760 if (dma->left_slot == chip->src_left_rec_slot) {
762 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
768 if (dma->regFCR == BA0_FCR0)
769 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
771 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
772 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
774 BA0_FCR_OF(dma->fifo_offset);
775 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
777 if (dma->regFCR == BA0_FCR0)
778 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
780 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
786 struct cs4281_dma *dma = runtime->private_data;
790 snd_cs4281_mode(chip, dma, runtime, 0, 1);
798 struct cs4281_dma *dma = runtime->private_data;
802 snd_cs4281_mode(chip, dma, runtime, 1, 1);
810 struct cs4281_dma *dma = runtime->private_data;
816 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
820 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
877 struct cs4281_dma *dma;
879 dma = &chip->dma[0];
880 dma->substream = substream;
881 dma->left_slot = 0;
882 dma->right_slot = 1;
883 runtime->private_data = dma;
896 struct cs4281_dma *dma;
898 dma = &chip->dma[1];
899 dma->substream = substream;
900 dma->left_slot = 10;
901 dma->right_slot = 11;
902 runtime->private_data = dma;
913 struct cs4281_dma *dma = substream->runtime->private_data;
915 dma->substream = NULL;
921 struct cs4281_dma *dma = substream->runtime->private_data;
923 dma->substream = NULL;
1553 struct cs4281_dma *dma = &chip->dma[tmp];
1554 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1555 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1556 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1557 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1558 dma->regDMR = BA0_DMR0 + (tmp * 8);
1559 dma->regDCR = BA0_DCR0 + (tmp * 8);
1560 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1561 dma->regFCR = BA0_FCR0 + (tmp * 4);
1562 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1563 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1564 snd_cs4281_pokeBA0(chip, dma->regFCR,
1568 BA0_FCR_OF(dma->fifo_offset));
1577 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1580 BA0_FCR_OF(chip->dma[0].fifo_offset);
1581 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1770 unsigned int status, dma, val;
1782 for (dma = 0; dma < 4; dma++)
1783 if (status & BA0_HISR_DMA(dma)) {
1784 cdma = &chip->dma[dma];