Lines Matching refs:cm
501 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
503 outl(data, cm->iobase + cmd);
506 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
508 return inl(cm->iobase + cmd);
512 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
514 outw(data, cm->iobase + cmd);
517 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
519 return inw(cm->iobase + cmd);
523 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
525 outb(data, cm->iobase + cmd);
528 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
530 return inb(cm->iobase + cmd);
534 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
537 val = oval = inl(cm->iobase + cmd);
541 outl(val, cm->iobase + cmd);
545 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
548 val = oval = inl(cm->iobase + cmd);
552 outl(val, cm->iobase + cmd);
557 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
560 val = oval = inb(cm->iobase + cmd);
564 outb(val, cm->iobase + cmd);
568 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
571 val = oval = inb(cm->iobase + cmd);
575 outb(val, cm->iobase + cmd);
650 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
661 snd_cmipci_write_b(cm, reg, rate>>8);
662 snd_cmipci_write_b(cm, reg, rate&0xff);
671 struct cmipci *cm = snd_pcm_substream_chip(substream);
673 mutex_lock(&cm->open_mutex);
674 if (cm->opened[CM_CH_PLAY]) {
675 mutex_unlock(&cm->open_mutex);
679 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
680 mutex_unlock(&cm->open_mutex);
685 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
687 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
688 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
689 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
714 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
717 if (!cm->can_multi_ch || !rec->ch)
723 if (cm->can_multi_ch) {
724 spin_lock_irq(&cm->reg_lock);
726 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
727 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
729 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
730 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
733 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
735 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
737 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
738 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
740 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
741 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
744 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
746 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
747 spin_unlock_irq(&cm->reg_lock);
757 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
773 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
774 dev_dbg(cm->card->dev, "cannot set dac channels\n");
788 spin_lock_irq(&cm->reg_lock);
792 snd_cmipci_write(cm, reg, rec->offset);
795 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
796 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
801 cm->ctrl &= ~val;
803 cm->ctrl |= val;
804 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
805 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
819 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
827 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
828 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
831 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
839 if (cm->can_96k) {
843 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
844 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
846 if (!rec->is_dac && cm->chip_version) {
848 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
850 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
854 spin_unlock_irq(&cm->reg_lock);
862 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
873 spin_lock(&cm->reg_lock);
878 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
879 cm->ctrl |= chen;
881 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
882 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
887 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
889 cm->ctrl &= ~chen;
890 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
891 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
896 cm->ctrl |= pause;
897 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
901 cm->ctrl &= ~pause;
902 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
908 spin_unlock(&cm->reg_lock);
915 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
926 rem = snd_cmipci_read_w(cm, reg);
930 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
936 ptr = snd_cmipci_read(cm, reg) - rec->offset;
951 struct cmipci *cm = snd_pcm_substream_chip(substream);
952 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
957 struct cmipci *cm = snd_pcm_substream_chip(substream);
958 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
970 struct cmipci *cm = snd_pcm_substream_chip(substream);
971 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
976 struct cmipci *cm = snd_pcm_substream_chip(substream);
977 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1111 static int save_mixer_state(struct cmipci *cm)
1113 if (! cm->mixer_insensitive) {
1121 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1126 cm->mixer_res_status[i] = val->value.integer.value[0];
1129 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1134 snd_ctl_notify(cm->card, event, &ctl->id);
1138 cm->mixer_insensitive = 1;
1145 static void restore_mixer_state(struct cmipci *cm)
1147 if (cm->mixer_insensitive) {
1154 cm->mixer_insensitive = 0; /* at first clear this;
1157 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1165 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1166 val->value.integer.value[0] = cm->mixer_res_status[i];
1170 snd_ctl_notify(cm->card, event, &ctl->id);
1178 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1182 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1184 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1186 if (cm->can_ac3_hw) {
1189 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1190 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1193 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1195 if (cm->chip_version == 33) {
1197 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1199 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1205 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1206 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1208 if (cm->can_ac3_hw) {
1211 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1212 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1214 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1215 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1218 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1219 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1220 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1225 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1232 if ((err = save_mixer_state(cm)) < 0)
1235 spin_lock_irq(&cm->reg_lock);
1236 cm->spdif_playback_avail = up;
1239 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1240 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1241 if (cm->spdif_playback_enabled)
1242 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1243 setup_ac3(cm, subs, do_ac3, rate);
1246 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1248 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1250 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1252 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1255 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1256 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1257 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1258 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1259 setup_ac3(cm, subs, 0, 0);
1261 spin_unlock_irq(&cm->reg_lock);
1273 struct cmipci *cm = snd_pcm_substream_chip(substream);
1280 if (do_spdif && cm->can_ac3_hw)
1281 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1282 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1284 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1290 struct cmipci *cm = snd_pcm_substream_chip(substream);
1293 if (cm->can_ac3_hw)
1294 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1297 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1299 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1310 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1320 snd_cmipci_write(cm, reg, val);
1324 set_dac_channels(cm, rec, 2);
1325 spin_lock_irq(&cm->reg_lock);
1326 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1329 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1330 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1333 if (cm->can_96k)
1335 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1338 cm->ctrl |= CM_CHEN0 << rec->ch;
1339 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1340 spin_unlock_irq(&cm->reg_lock);
1345 spin_lock_irq(&cm->reg_lock);
1346 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1348 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1349 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1350 spin_unlock_irq(&cm->reg_lock);
1358 struct cmipci *cm = snd_pcm_substream_chip(substream);
1359 setup_spdif_playback(cm, substream, 0, 0);
1360 restore_mixer_state(cm);
1361 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1367 struct cmipci *cm = snd_pcm_substream_chip(substream);
1368 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1375 struct cmipci *cm = snd_pcm_substream_chip(substream);
1376 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1382 struct cmipci *cm = snd_pcm_substream_chip(substream);
1384 spin_lock_irq(&cm->reg_lock);
1385 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1386 if (cm->can_96k) {
1388 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1390 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1393 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1395 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1397 spin_unlock_irq(&cm->reg_lock);
1399 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1404 struct cmipci *cm = snd_pcm_substream_chip(subs);
1406 spin_lock_irq(&cm->reg_lock);
1407 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1408 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1409 spin_unlock_irq(&cm->reg_lock);
1420 struct cmipci *cm = dev_id;
1424 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1429 spin_lock(&cm->reg_lock);
1434 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1435 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1436 spin_unlock(&cm->reg_lock);
1438 if (cm->rmidi && (status & CM_UARTINT))
1439 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1441 if (cm->pcm) {
1442 if ((status & CM_CHINT0) && cm->channel[0].running)
1443 snd_pcm_period_elapsed(cm->channel[0].substream);
1444 if ((status & CM_CHINT1) && cm->channel[1].running)
1445 snd_pcm_period_elapsed(cm->channel[1].substream);
1586 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1595 mutex_lock(&cm->open_mutex);
1596 if (cm->opened[ch]) {
1597 mutex_unlock(&cm->open_mutex);
1600 cm->opened[ch] = mode;
1601 cm->channel[ch].substream = subs;
1604 cm->channel[ch].is_dac = 0;
1605 spin_lock_irq(&cm->reg_lock);
1606 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1607 spin_unlock_irq(&cm->reg_lock);
1609 mutex_unlock(&cm->open_mutex);
1613 static void close_device_check(struct cmipci *cm, int mode)
1617 mutex_lock(&cm->open_mutex);
1618 if (cm->opened[ch] == mode) {
1619 if (cm->channel[ch].substream) {
1620 snd_cmipci_ch_reset(cm, ch);
1621 cm->channel[ch].running = 0;
1622 cm->channel[ch].substream = NULL;
1624 cm->opened[ch] = 0;
1625 if (! cm->channel[ch].is_dac) {
1627 cm->channel[ch].is_dac = 1;
1628 spin_lock_irq(&cm->reg_lock);
1629 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1630 spin_unlock_irq(&cm->reg_lock);
1633 mutex_unlock(&cm->open_mutex);
1641 struct cmipci *cm = snd_pcm_substream_chip(substream);
1645 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1648 if (cm->chip_version == 68) {
1652 } else if (cm->chip_version == 55) {
1661 cm->dig_pcm_status = cm->dig_status;
1667 struct cmipci *cm = snd_pcm_substream_chip(substream);
1671 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1674 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1677 } else if (cm->chip_version == 55) {
1691 struct cmipci *cm = snd_pcm_substream_chip(substream);
1695 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1698 mutex_lock(&cm->open_mutex);
1699 if (! cm->opened[CM_CH_PLAY]) {
1700 if (cm->can_multi_ch) {
1701 runtime->hw.channels_max = cm->max_channels;
1702 if (cm->max_channels == 4)
1704 else if (cm->max_channels == 6)
1706 else if (cm->max_channels == 8)
1710 mutex_unlock(&cm->open_mutex);
1711 if (cm->chip_version == 68) {
1715 } else if (cm->chip_version == 55) {
1729 struct cmipci *cm = snd_pcm_substream_chip(substream);
1733 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1735 if (cm->can_ac3_hw) {
1737 if (cm->chip_version >= 37) {
1741 if (cm->can_96k) {
1750 cm->dig_pcm_status = cm->dig_status;
1756 struct cmipci *cm = snd_pcm_substream_chip(substream);
1760 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1763 if (cm->can_96k && !(cm->chip_version == 68)) {
1778 struct cmipci *cm = snd_pcm_substream_chip(substream);
1779 close_device_check(cm, CM_OPEN_PLAYBACK);
1785 struct cmipci *cm = snd_pcm_substream_chip(substream);
1786 close_device_check(cm, CM_OPEN_CAPTURE);
1792 struct cmipci *cm = snd_pcm_substream_chip(substream);
1793 close_device_check(cm, CM_OPEN_PLAYBACK2);
1794 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1800 struct cmipci *cm = snd_pcm_substream_chip(substream);
1801 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1807 struct cmipci *cm = snd_pcm_substream_chip(substream);
1808 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1865 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1870 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1877 pcm->private_data = cm;
1880 cm->pcm = pcm;
1883 &cm->pci->dev, 64*1024, 128*1024);
1888 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1893 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1899 pcm->private_data = cm;
1902 cm->pcm2 = pcm;
1905 &cm->pci->dev, 64*1024, 128*1024);
1910 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1915 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1922 pcm->private_data = cm;
1925 cm->pcm_spdif = pcm;
1928 &cm->pci->dev, 64*1024, 128*1024);
1931 snd_pcm_alt_chmaps, cm->max_channels, 0,
2016 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2021 spin_lock_irq(&cm->reg_lock);
2022 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2027 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2032 spin_unlock_irq(&cm->reg_lock);
2039 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2056 spin_lock_irq(&cm->reg_lock);
2057 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2062 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2063 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2068 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2070 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2071 spin_unlock_irq(&cm->reg_lock);
2098 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2103 spin_lock_irq(&cm->reg_lock);
2104 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2105 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2106 spin_unlock_irq(&cm->reg_lock);
2117 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2123 spin_lock_irq(&cm->reg_lock);
2124 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2125 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2133 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2134 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2135 spin_unlock_irq(&cm->reg_lock);
2188 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2193 spin_lock_irq(&cm->reg_lock);
2194 oreg = inb(cm->iobase + reg.left_reg);
2205 spin_unlock_irq(&cm->reg_lock);
2212 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2217 spin_lock_irq(&cm->reg_lock);
2218 oreg = inb(cm->iobase + reg.left_reg);
2231 outb(nreg, cm->iobase + reg.left_reg);
2232 spin_unlock_irq(&cm->reg_lock);
2242 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2249 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2250 if (cm->mixer_insensitive) {
2317 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2319 spin_lock_irq(&cm->reg_lock);
2320 if (args->ac3_sensitive && cm->mixer_insensitive) {
2322 spin_unlock_irq(&cm->reg_lock);
2326 val = inb(cm->iobase + args->reg);
2328 val = snd_cmipci_read(cm, args->reg);
2330 spin_unlock_irq(&cm->reg_lock);
2350 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2352 spin_lock_irq(&cm->reg_lock);
2353 if (args->ac3_sensitive && cm->mixer_insensitive) {
2355 spin_unlock_irq(&cm->reg_lock);
2359 val = inb(cm->iobase + args->reg);
2361 val = snd_cmipci_read(cm, args->reg);
2371 outb((unsigned char)val, cm->iobase + args->reg);
2373 snd_cmipci_write(cm, args->reg, val);
2375 spin_unlock_irq(&cm->reg_lock);
2480 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2486 cm->chip_version >= 39 ? 3 : 2, texts);
2489 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2492 if (cm->chip_version >= 39) {
2493 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2497 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2506 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2508 spin_lock_irq(&cm->reg_lock);
2509 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2510 spin_unlock_irq(&cm->reg_lock);
2517 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2520 spin_lock_irq(&cm->reg_lock);
2522 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2524 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2526 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2528 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2529 spin_unlock_irq(&cm->reg_lock);
2544 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2546 spin_lock_irq(&cm->reg_lock);
2548 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2549 spin_unlock_irq(&cm->reg_lock);
2556 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2559 spin_lock_irq(&cm->reg_lock);
2561 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2563 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2564 spin_unlock_irq(&cm->reg_lock);
2631 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2639 if (snd_BUG_ON(!cm || !cm->card))
2642 card = cm->card;
2646 spin_lock_irq(&cm->reg_lock);
2647 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2648 spin_unlock_irq(&cm->reg_lock);
2651 if (cm->chip_version == 68) { // 8768 has no PCM volume
2656 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2663 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2667 if (! cm->can_multi_ch) {
2668 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2672 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2673 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2676 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2680 if (cm->can_ac3_hw) {
2681 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2684 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2687 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2691 if (cm->chip_version <= 37) {
2694 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2700 if (cm->chip_version >= 39) {
2703 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2714 if (cm->chip_version < 39) {
2715 err = snd_ctl_add(cm->card,
2716 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2727 ctl = snd_ctl_find_id(cm->card, &elem_id);
2729 cm->mixer_res_ctl[idx] = ctl;
2743 struct cmipci *cm = entry->private_data;
2746 snd_iprintf(buffer, "%s\n", cm->card->longname);
2750 v = inb(cm->iobase + i);
2758 static void snd_cmipci_proc_init(struct cmipci *cm)
2760 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2777 static void query_chip(struct cmipci *cm)
2782 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2785 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2788 cm->chip_version = 33;
2789 if (cm->do_soft_ac3)
2790 cm->can_ac3_sw = 1;
2792 cm->can_ac3_hw = 1;
2795 cm->chip_version = 37;
2796 cm->can_ac3_hw = 1;
2799 cm->chip_version = 39;
2800 cm->can_ac3_hw = 1;
2803 cm->max_channels = 2;
2806 cm->chip_version = 39;
2808 cm->max_channels = 6;
2810 cm->max_channels = 4;
2812 cm->chip_version = 68;
2813 cm->max_channels = 8;
2814 cm->can_96k = 1;
2816 cm->chip_version = 55;
2817 cm->max_channels = 6;
2818 cm->can_96k = 1;
2820 cm->can_ac3_hw = 1;
2821 cm->can_multi_ch = 1;
2826 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2849 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2853 cm->gameport = gp = gameport_allocate_port();
2855 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2860 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2861 gameport_set_dev_parent(gp, &cm->pci->dev);
2865 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2867 gameport_register_port(cm->gameport);
2872 static void snd_cmipci_free_gameport(struct cmipci *cm)
2874 if (cm->gameport) {
2875 struct resource *r = gameport_get_port_data(cm->gameport);
2877 gameport_unregister_port(cm->gameport);
2878 cm->gameport = NULL;
2880 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2885 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2886 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2889 static int snd_cmipci_free(struct cmipci *cm)
2891 if (cm->irq >= 0) {
2892 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2893 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2894 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2895 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2896 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2897 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2898 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2901 snd_cmipci_mixer_write(cm, 0, 0);
2903 free_irq(cm->irq, cm);
2906 snd_cmipci_free_gameport(cm);
2907 pci_release_regions(cm->pci);
2908 pci_disable_device(cm->pci);
2909 kfree(cm);
2915 struct cmipci *cm = device->device_data;
2916 return snd_cmipci_free(cm);
2919 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2929 if (cm->chip_version >= 39) {
2931 iosynth = cm->iobase + CM_REG_FM_PCI;
2932 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2939 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2949 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2951 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2953 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2955 dev_err(cm->card->dev,
2962 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2968 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2969 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2976 struct cmipci *cm;
2996 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2997 if (cm == NULL) {
3002 spin_lock_init(&cm->reg_lock);
3003 mutex_init(&cm->open_mutex);
3004 cm->device = pci->device;
3005 cm->card = card;
3006 cm->pci = pci;
3007 cm->irq = -1;
3008 cm->channel[0].ch = 0;
3009 cm->channel[1].ch = 1;
3010 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3013 kfree(cm);
3017 cm->iobase = pci_resource_start(pci, 0);
3020 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3022 snd_cmipci_free(cm);
3025 cm->irq = pci->irq;
3026 card->sync_irq = cm->irq;
3028 pci_set_master(cm->pci);
3034 cm->chip_version = 0;
3035 cm->max_channels = 2;
3036 cm->do_soft_ac3 = soft_ac3[dev];
3040 query_chip(cm);
3042 if (cm->can_multi_ch)
3043 sprintf(cm->card->driver + strlen(cm->card->driver),
3044 "-MC%d", cm->max_channels);
3045 else if (cm->can_ac3_sw)
3046 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3048 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3049 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3052 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3054 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3058 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3059 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3060 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3061 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3062 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3063 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3064 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3066 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3067 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3069 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3071 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3073 if (cm->chip_version) {
3074 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3075 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3078 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3085 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3091 if (cm->chip_version < 68) {
3094 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3119 if (cm->chip_version < 68)
3120 sprintf(modelstr, " (model %d)", cm->chip_version);
3124 card->shortname, modelstr, cm->iobase, cm->irq);
3126 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3127 snd_cmipci_free(cm);
3131 if (cm->chip_version >= 39) {
3132 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3135 iomidi = cm->iobase + CM_REG_MPU_PCI;
3151 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3153 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3155 dev_err(cm->card->dev,
3158 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3165 if (cm->chip_version < 68) {
3166 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3172 snd_cmipci_mixer_write(cm, 0, 0);
3174 snd_cmipci_proc_init(cm);
3178 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3181 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3184 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3186 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3191 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3200 -1, &cm->rmidi)) < 0) {
3201 dev_err(cm->card->dev,
3208 snd_cmipci_set_pll(cm, rates[val], val);
3213 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3216 if (snd_cmipci_create_gameport(cm, dev) < 0)
3217 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3219 *rcmipci = cm;
3233 struct cmipci *cm;
3262 err = snd_cmipci_create(card, pci, dev, &cm);
3266 card->private_data = cm;
3313 struct cmipci *cm = card->private_data;
3320 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3322 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3325 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3332 struct cmipci *cm = card->private_data;
3336 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3337 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3338 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3339 snd_cmipci_mixer_write(cm, 0, 0);
3343 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3345 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);