Lines Matching defs:CM_REG_FUNCTRL1
83 #define CM_REG_FUNCTRL1 0x04
647 * at the register CM_REG_FUNCTRL1 (0x04).
819 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
827 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1240 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1242 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1256 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1258 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1326 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1329 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1385 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1407 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
2402 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2403 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2408 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2414 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2427 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2466 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2469 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2865 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2880 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2898 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3064 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3078 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3153 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3158 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3217 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3292 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,