Lines Matching refs:chip
30 * It is quite likely that the AZF3328 chip is the PCI cousin of the
31 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
33 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
45 * Note that "conformant" != "compliant"!! this chip's mixer register layout
76 * - single chip low cost solution (128 pin QFP)
77 * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip]
85 * [TDA1517P chip]
109 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
398 snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
400 outb(value, chip->ctrl_io + reg);
404 snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
406 return inb(chip->ctrl_io + reg);
410 snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg)
412 return inw(chip->ctrl_io + reg);
416 snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
418 outw(value, chip->ctrl_io + reg);
422 snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
424 outl(value, chip->ctrl_io + reg);
428 snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
430 outb(value, chip->game_io + reg);
434 snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
436 outw(value, chip->game_io + reg);
440 snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
442 return inb(chip->game_io + reg);
446 snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
448 return inw(chip->game_io + reg);
452 snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
454 outw(value, chip->mixer_io + reg);
458 snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
460 return inw(chip->mixer_io + reg);
466 snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip,
470 unsigned long portbase = chip->mixer_io + reg + 1;
482 snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip,
487 chip,
494 snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip,
499 chip,
506 snd_azf3328_mixer_reset(const struct snd_azf3328 *chip)
511 snd_azf3328_mixer_mute_control_master(chip, 1);
512 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
518 snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip,
522 dev_warn(chip->card->dev,
653 const struct snd_azf3328 *chip = ac97->private_data;
658 dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n",
664 reg_val = snd_azf3328_mixer_inw(chip,
675 snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H);
704 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read");
713 const struct snd_azf3328 *chip = ac97->private_data;
717 dev_dbg(chip->card->dev,
725 chip,
752 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write");
756 snd_azf3328_mixer_new(struct snd_azf3328 *chip)
770 ac97.private_data = chip;
771 ac97.pci = chip->pci;
779 rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus);
781 rc = snd_ac97_mixer(bus, &ac97, &chip->ac97);
788 dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc);
797 snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
804 unsigned long portbase = chip->mixer_io + reg;
938 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
944 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
955 dev_dbg(chip->card->dev,
967 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
972 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
987 chip, reg.reg, nreg >> 8, nreg & 0xff,
992 snd_azf3328_mixer_outw(chip, reg.reg, nreg);
994 dev_dbg(chip->card->dev,
998 nreg, snd_azf3328_mixer_inw(chip, reg.reg));
1047 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
1052 val = snd_azf3328_mixer_inw(chip, reg.reg);
1059 dev_dbg(chip->card->dev,
1070 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
1075 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
1089 snd_azf3328_mixer_outw(chip, reg.reg, val);
1092 dev_dbg(chip->card->dev,
1172 snd_azf3328_mixer_new(struct snd_azf3328 *chip)
1179 if (snd_BUG_ON(!chip || !chip->card))
1182 card = chip->card;
1185 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
1189 snd_azf3328_mixer_outw(chip,
1198 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
1296 snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
1303 chip->shadow_reg_ctrl_6AH |= bitmask;
1305 chip->shadow_reg_ctrl_6AH &= ~bitmask;
1306 dev_dbg(chip->card->dev,
1308 bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
1309 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
1313 snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
1315 dev_dbg(chip->card->dev, "codec_enable %d\n", enable);
1319 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
1324 snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
1329 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1332 dev_dbg(chip->card->dev,
1356 ((!chip->codecs[peer_codecs[codec_type].other1]
1358 && (!chip->codecs[peer_codecs[codec_type].other2]
1362 snd_azf3328_ctrl_enable_codecs(chip, enable);
1373 snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
1402 dev_dbg(chip->card->dev,
1444 snd_azf3328_codec_setdmaa(chip, codec,
1453 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1463 dev_dbg(chip->card->dev, "START PCM %s\n", codec->name);
1469 chip, 1
1490 snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr,
1520 snd_azf3328_ctrl_codec_activity(chip, codec->type, 1);
1526 chip, 0
1530 dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name);
1533 dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name);
1545 dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name);
1551 chip, 1
1571 snd_azf3328_ctrl_codec_activity(chip, codec->type, 0);
1577 chip, 0
1581 dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name);
1584 dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name);
1633 snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
1638 chip->game_io+IDX_GAME_HWCONFIG,
1645 snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
1650 chip->game_io+IDX_GAME_HWCONFIG,
1657 snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
1662 chip->game_io+IDX_GAME_HWCONFIG,
1667 chip->game_io+IDX_GAME_HWCONFIG,
1674 snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
1677 chip, IO_6A_SOMETHING2_GAMEPORT, enable
1682 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1688 dev_dbg(chip->card->dev, "gameport irq\n");
1691 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
1697 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1700 dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode);
1711 snd_azf3328_gameport_set_counter_frequency(chip,
1713 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
1721 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1723 dev_dbg(chip->card->dev, "gameport_close\n");
1724 snd_azf3328_gameport_set_counter_frequency(chip,
1726 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1735 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1740 if (snd_BUG_ON(!chip))
1743 spin_lock_irqsave(&chip->reg_lock, flags);
1744 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
1757 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
1759 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
1762 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1764 chip->axes[i] = snd_azf3328_game_inw(
1765 chip, IDX_GAME_AXIS_VALUE
1777 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1779 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
1780 spin_unlock_irqrestore(&chip->reg_lock, flags);
1782 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
1783 axes[i] = chip->axes[i];
1788 dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n",
1795 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
1799 chip->gameport = gp = gameport_allocate_port();
1801 dev_err(chip->card->dev, "cannot alloc memory for gameport\n");
1806 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1807 gameport_set_dev_parent(gp, &chip->pci->dev);
1808 gp->io = chip->game_io;
1809 gameport_set_port_data(gp, chip);
1817 snd_azf3328_gameport_legacy_address_enable(chip, 0);
1819 snd_azf3328_gameport_set_counter_frequency(chip,
1821 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1823 gameport_register_port(chip->gameport);
1829 snd_azf3328_gameport_free(struct snd_azf3328 *chip)
1831 if (chip->gameport) {
1832 gameport_unregister_port(chip->gameport);
1833 chip->gameport = NULL;
1835 snd_azf3328_gameport_irq_enable(chip, 0);
1839 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
1841 snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
1843 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1845 dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n");
1852 snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which)
1854 dev_dbg(chip->card->dev,
1860 snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip,
1885 dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n",
1891 dev_warn(chip->card->dev, "irq handler problem!\n");
1893 snd_azf3328_irq_log_unknown_type(chip, which);
1900 struct snd_azf3328 *chip = dev_id;
1904 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
1913 dev_dbg(chip->card->dev,
1919 /* dev_dbg(chip->card->dev, "timer %ld\n",
1920 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
1923 if (chip->timer)
1924 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1926 spin_lock(&chip->reg_lock);
1927 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
1928 spin_unlock(&chip->reg_lock);
1929 dev_dbg(chip->card->dev, "timer IRQ\n");
1933 snd_azf3328_pcm_interrupt(chip, chip->codecs, status);
1936 snd_azf3328_gameport_interrupt(chip);
1941 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1945 dev_dbg(chip->card->dev, "MPU401 IRQ\n");
2019 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
2021 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
2090 snd_azf3328_pcm(struct snd_azf3328 *chip)
2098 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD,
2107 pcm->private_data = chip;
2109 strcpy(pcm->name, chip->card->shortname);
2111 chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
2112 chip->pcm[AZF_CODEC_CAPTURE] = pcm;
2114 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
2117 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT,
2124 pcm->private_data = chip;
2126 strcpy(pcm->name, chip->card->shortname);
2127 chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
2129 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
2150 struct snd_azf3328 *chip;
2154 chip = snd_timer_chip(timer);
2161 dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay);
2164 dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay);
2166 spin_lock_irqsave(&chip->reg_lock, flags);
2167 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay);
2168 spin_unlock_irqrestore(&chip->reg_lock, flags);
2175 struct snd_azf3328 *chip;
2178 chip = snd_timer_chip(timer);
2179 spin_lock_irqsave(&chip->reg_lock, flags);
2187 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04);
2188 spin_unlock_irqrestore(&chip->reg_lock, flags);
2212 snd_azf3328_timer(struct snd_azf3328 *chip, int device)
2220 tid.card = chip->card->number;
2227 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
2232 timer->private_data = chip;
2235 chip->timer = timer;
2248 snd_azf3328_free(struct snd_azf3328 *chip)
2250 if (chip->irq < 0)
2253 snd_azf3328_mixer_reset(chip);
2255 snd_azf3328_timer_stop(chip->timer);
2256 snd_azf3328_gameport_free(chip);
2259 if (chip->irq >= 0)
2260 free_irq(chip->irq, chip);
2261 pci_release_regions(chip->pci);
2262 pci_disable_device(chip->pci);
2264 kfree(chip);
2271 struct snd_azf3328 *chip = device->device_data;
2272 return snd_azf3328_free(chip);
2299 snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
2303 dev_dbg(chip->card->dev,
2306 chip->ctrl_io, chip->game_io, chip->mpu_io,
2307 chip->opl3_io, chip->mixer_io, chip->irq);
2309 dev_dbg(chip->card->dev,
2311 snd_azf3328_game_inb(chip, 0),
2312 snd_azf3328_game_inb(chip, 1),
2313 snd_azf3328_game_inb(chip, 2),
2314 snd_azf3328_game_inb(chip, 3),
2315 snd_azf3328_game_inb(chip, 4),
2316 snd_azf3328_game_inb(chip, 5));
2319 dev_dbg(chip->card->dev,
2320 "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
2323 dev_dbg(chip->card->dev,
2328 dev_dbg(chip->card->dev,
2340 dev_dbg(chip->card->dev,
2342 tmp, snd_azf3328_ctrl_inw(chip, tmp));
2345 dev_dbg(chip->card->dev,
2347 tmp, snd_azf3328_mixer_inw(chip, tmp));
2356 struct snd_azf3328 *chip;
2371 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2372 if (chip == NULL) {
2376 spin_lock_init(&chip->reg_lock);
2377 chip->card = card;
2378 chip->pci = pci;
2379 chip->irq = -1;
2395 chip->ctrl_io = pci_resource_start(pci, 0);
2396 chip->game_io = pci_resource_start(pci, 1);
2397 chip->mpu_io = pci_resource_start(pci, 2);
2398 chip->opl3_io = pci_resource_start(pci, 3);
2399 chip->mixer_io = pci_resource_start(pci, 4);
2401 codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK];
2402 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
2403 codec_setup->lock = &chip->reg_lock;
2407 codec_setup = &chip->codecs[AZF_CODEC_CAPTURE];
2408 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
2409 codec_setup->lock = &chip->reg_lock;
2413 codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT];
2414 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
2415 codec_setup->lock = &chip->reg_lock;
2420 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2425 chip->irq = pci->irq;
2426 card->sync_irq = chip->irq;
2429 snd_azf3328_debug_show_ports(chip);
2431 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2436 err = snd_azf3328_mixer_new(chip);
2447 &chip->codecs[codec_type];
2452 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
2460 *rchip = chip;
2466 if (chip)
2467 snd_azf3328_free(chip);
2479 struct snd_azf3328 *chip;
2501 err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
2505 card->private_data = chip;
2511 MPU401_HW_AZT2320, chip->mpu_io,
2513 -1, &chip->rmidi
2517 chip->mpu_io
2522 err = snd_azf3328_timer(chip, 0);
2526 err = snd_azf3328_pcm(chip);
2530 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
2533 chip->opl3_io, chip->opl3_io+2
2543 opl3->private_data = chip;
2547 card->shortname, chip->ctrl_io, chip->irq);
2565 snd_azf3328_gameport(chip, dev);
2589 snd_azf3328_suspend_regs(const struct snd_azf3328 *chip,
2596 dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n",
2604 snd_azf3328_resume_regs(const struct snd_azf3328 *chip,
2614 dev_dbg(chip->card->dev,
2623 snd_azf3328_suspend_ac97(struct snd_azf3328 *chip)
2626 snd_ac97_suspend(chip->ac97);
2628 snd_azf3328_suspend_regs(chip, chip->mixer_io,
2629 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
2632 snd_azf3328_mixer_mute_control_master(chip, 1);
2633 snd_azf3328_mixer_mute_control_pcm(chip, 1);
2638 snd_azf3328_resume_ac97(const struct snd_azf3328 *chip)
2641 snd_ac97_resume(chip->ac97);
2643 snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io,
2644 ARRAY_SIZE(chip->saved_regs_mixer));
2650 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
2658 struct snd_azf3328 *chip = card->private_data;
2663 snd_azf3328_suspend_ac97(chip);
2665 snd_azf3328_suspend_regs(chip, chip->ctrl_io,
2666 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
2669 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
2670 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
2672 snd_azf3328_suspend_regs(chip, chip->game_io,
2673 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
2674 snd_azf3328_suspend_regs(chip, chip->mpu_io,
2675 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
2676 snd_azf3328_suspend_regs(chip, chip->opl3_io,
2677 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
2685 const struct snd_azf3328 *chip = card->private_data;
2687 snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io,
2688 ARRAY_SIZE(chip->saved_regs_game));
2689 snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io,
2690 ARRAY_SIZE(chip->saved_regs_mpu));
2691 snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io,
2692 ARRAY_SIZE(chip->saved_regs_opl3));
2694 snd_azf3328_resume_ac97(chip);
2696 snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io,
2697 ARRAY_SIZE(chip->saved_regs_ctrl));