Lines Matching refs:snd_opl3sa2_write
200 static void snd_opl3sa2_write(struct snd_opl3sa2 *chip, unsigned char reg, unsigned char value)
246 snd_opl3sa2_write(chip, OPL3SA2_MISC, tmp ^ 7);
253 snd_opl3sa2_write(chip, OPL3SA2_MIC, 0x8a);
258 snd_opl3sa2_write(chip, OPL3SA2_MIC, 0x9f);
261 snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0);
264 snd_opl3sa2_write(chip, OPL3SA2_SYS_CTRL, (chip->ymode << 4));
267 snd_opl3sa2_write(chip, OPL3SA2_SYS_CTRL, 0x00);
269 snd_opl3sa2_write(chip, OPL3SA2_IRQ_CONFIG, 0x0d); /* Interrupt Channel Configuration - IRQ A = OPL3 + MPU + WSS */
271 snd_opl3sa2_write(chip, OPL3SA2_DMA_CONFIG, 0x03); /* DMA Configuration - DMA A = WSS-R + WSS-P */
273 snd_opl3sa2_write(chip, OPL3SA2_DMA_CONFIG, 0x21); /* DMA Configuration - DMA B = WSS-R, DMA A = WSS-P */
275 snd_opl3sa2_write(chip, OPL3SA2_MISC, 0x80 | (tmp & 7)); /* Miscellaneous - default */
277 snd_opl3sa2_write(chip, OPL3SA3_DGTL_DOWN, 0x00); /* Digital Block Partial Power Down - default */
278 snd_opl3sa2_write(chip, OPL3SA3_ANLG_DOWN, 0x00); /* Analog Block Partial Power Down - default */
547 snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D3);
563 snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0);
568 snd_opl3sa2_write(chip, i, chip->ctlregs[i]);
572 snd_opl3sa2_write(chip, i, chip->ctlregs[i]);