Lines Matching refs:bus
16 static void azx_clear_corbrp(struct hdac_bus *bus)
21 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
26 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
27 snd_hdac_chip_readw(bus, CORBRP));
29 snd_hdac_chip_writew(bus, CORBRP, 0);
31 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
36 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
37 snd_hdac_chip_readw(bus, CORBRP));
42 * @bus: HD-audio core bus
44 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
46 struct azx *chip = bus_to_azx(bus);
48 WARN_ON_ONCE(!bus->rb.area);
50 spin_lock_irq(&bus->reg_lock);
52 bus->corb.addr = bus->rb.addr;
53 bus->corb.buf = (__le32 *)bus->rb.area;
54 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
55 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
58 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
60 snd_hdac_chip_writew(bus, CORBWP, 0);
63 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
65 snd_hdac_chip_writew(bus, CORBRP, 0);
66 else if (!bus->corbrp_self_clear)
67 azx_clear_corbrp(bus);
70 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
72 snd_hdac_chip_readb(bus, CORBCTL);
75 bus->rirb.addr = bus->rb.addr + 2048;
76 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
77 bus->rirb.wp = bus->rirb.rp = 0;
78 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
79 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
80 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
83 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
85 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
87 snd_hdac_chip_writew(bus, RINTCNT, 1);
90 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN);
91 snd_hdac_chip_readb(bus, RIRBCTL);
94 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
96 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
97 spin_unlock_irq(&bus->reg_lock);
102 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
107 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
112 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
119 * @bus: HD-audio core bus
121 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
123 spin_lock_irq(&bus->reg_lock);
125 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
126 snd_hdac_chip_writeb(bus, CORBCTL, 0);
127 spin_unlock_irq(&bus->reg_lock);
129 hdac_wait_for_cmd_dmas(bus);
131 spin_lock_irq(&bus->reg_lock);
133 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
134 spin_unlock_irq(&bus->reg_lock);
161 * @bus: HD-audio core bus
166 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
171 spin_lock_irq(&bus->reg_lock);
173 bus->last_cmd[azx_command_addr(val)] = val;
176 wp = snd_hdac_chip_readw(bus, CORBWP);
179 spin_unlock_irq(&bus->reg_lock);
185 rp = snd_hdac_chip_readw(bus, CORBRP);
188 spin_unlock_irq(&bus->reg_lock);
192 bus->rirb.cmds[addr]++;
193 bus->corb.buf[wp] = cpu_to_le32(val);
194 snd_hdac_chip_writew(bus, CORBWP, wp);
196 spin_unlock_irq(&bus->reg_lock);
206 * @bus: HD-audio core bus
209 * The caller needs bus->reg_lock spinlock before calling this.
211 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
217 wp = snd_hdac_chip_readw(bus, RIRBWP);
223 if (wp == bus->rirb.wp)
225 bus->rirb.wp = wp;
227 while (bus->rirb.rp != wp) {
228 bus->rirb.rp++;
229 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
231 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
232 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
233 res = le32_to_cpu(bus->rirb.buf[rp]);
236 snd_hdac_bus_queue_event(bus, res, res_ex);
237 else if (bus->rirb.cmds[addr]) {
238 bus->rirb.res[addr] = res;
239 bus->rirb.cmds[addr]--;
240 if (!bus->rirb.cmds[addr] &&
241 waitqueue_active(&bus->rirb_wq))
242 wake_up(&bus->rirb_wq);
244 dev_err_ratelimited(bus->dev,
246 res, res_ex, bus->last_cmd[addr]);
254 * @bus: HD-audio core bus
260 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
272 spin_lock_irq(&bus->reg_lock);
273 if (!bus->polling_mode)
274 prepare_to_wait(&bus->rirb_wq, &wait,
276 if (bus->polling_mode)
277 snd_hdac_bus_update_rirb(bus);
278 if (!bus->rirb.cmds[addr]) {
280 *res = bus->rirb.res[addr]; /* the last value */
281 if (!bus->polling_mode)
282 finish_wait(&bus->rirb_wq, &wait);
283 spin_unlock_irq(&bus->reg_lock);
286 spin_unlock_irq(&bus->reg_lock);
290 if (!bus->polling_mode) {
292 } else if (bus->needs_damn_long_delay ||
295 dev_dbg_ratelimited(bus->dev,
297 bus->last_cmd[addr]);
307 if (!bus->polling_mode)
308 finish_wait(&bus->rirb_wq, &wait);
317 * @bus: the pointer to bus object
321 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
327 offset = snd_hdac_chip_readw(bus, LLCH);
331 cur_cap = _snd_hdac_chip_readl(bus, offset);
333 dev_dbg(bus->dev, "Capability version: 0x%x\n",
336 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
340 dev_dbg(bus->dev, "Invalid capability reg read\n");
346 dev_dbg(bus->dev, "Found ML capability\n");
347 bus->mlcap = bus->remap_addr + offset;
351 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
352 bus->gtscap = bus->remap_addr + offset;
357 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
358 bus->ppcap = bus->remap_addr + offset;
363 dev_dbg(bus->dev, "Found SPB capability\n");
364 bus->spbcap = bus->remap_addr + offset;
369 dev_dbg(bus->dev, "Found DRSM capability\n");
370 bus->drsmcap = bus->remap_addr + offset;
374 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
382 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
401 * @bus: HD-audio core bus
405 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
410 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
413 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
421 * @bus: HD-audio core bus
425 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
429 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
432 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
438 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
444 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
445 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
448 snd_hdac_bus_enter_link_reset(bus);
456 snd_hdac_bus_exit_link_reset(bus);
463 if (!snd_hdac_chip_readb(bus, GCTL)) {
464 dev_dbg(bus->dev, "controller not ready!\n");
469 if (!bus->codec_mask) {
470 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
471 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
479 static void azx_int_enable(struct hdac_bus *bus)
482 snd_hdac_chip_updatel(bus, INTCTL,
488 static void azx_int_disable(struct hdac_bus *bus)
493 list_for_each_entry(azx_dev, &bus->stream_list, list)
497 snd_hdac_chip_writeb(bus, INTCTL, 0);
500 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
504 static void azx_int_clear(struct hdac_bus *bus)
507 struct azx *chip = bus_to_azx(bus);
510 list_for_each_entry(azx_dev, &bus->stream_list, list) {
518 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
522 snd_hdac_chip_updateb(bus, RIRBSTS, ~RIRB_INT_MASK, 0);
524 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
527 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
532 * @bus: HD-audio core bus
535 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
537 if (bus->chip_init)
541 snd_hdac_bus_reset_link(bus, full_reset);
544 azx_int_clear(bus);
547 snd_hdac_bus_init_cmd_io(bus);
550 azx_int_enable(bus);
553 if (bus->use_posbuf && bus->posbuf.addr) {
554 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
555 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
558 bus->chip_init = true;
566 * @bus: HD-audio core bus
568 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
570 if (!bus->chip_init)
574 azx_int_disable(bus);
575 azx_int_clear(bus);
578 snd_hdac_bus_stop_cmd_io(bus);
581 if (bus->posbuf.addr) {
582 snd_hdac_chip_writel(bus, DPLBASE, 0);
583 snd_hdac_chip_writel(bus, DPUBASE, 0);
586 bus->chip_init = false;
592 * @bus: HD-audio core bus
598 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
605 struct azx *chip = bus_to_azx(bus);
607 list_for_each_entry(azx_dev, &bus->stream_list, list) {
621 ack(bus, azx_dev);
630 * @bus: HD-audio core bus
635 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
639 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
642 list_for_each_entry(s, &bus->stream_list, list) {
644 err = snd_dma_alloc_pages(dma_type, bus->dev,
654 err = snd_dma_alloc_pages(dma_type, bus->dev,
655 num_streams * 8, &bus->posbuf);
658 list_for_each_entry(s, &bus->stream_list, list)
659 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
662 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
668 * @bus: HD-audio core bus
670 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
674 list_for_each_entry(s, &bus->stream_list, list) {
679 if (bus->rb.area)
680 snd_dma_free_pages(&bus->rb);
681 if (bus->posbuf.area)
682 snd_dma_free_pages(&bus->posbuf);