Lines Matching refs:data
34 u32 data;
41 data = be32_to_cpu(reg);
43 data = (data & V3_CLOCK_RATE_MASK) >> V3_CLOCK_RATE_SHIFT;
44 if (data >= ARRAY_SIZE(snd_motu_clock_rates))
47 *rate = snd_motu_clock_rates[data];
56 u32 data;
71 data = be32_to_cpu(reg);
73 data &= ~(V3_CLOCK_RATE_MASK | V3_FETCH_PCM_FRAMES);
74 data |= i << V3_CLOCK_RATE_SHIFT;
76 need_to_wait = data != be32_to_cpu(reg);
78 reg = cpu_to_be32(data);
100 static int detect_clock_source_828mk3(struct snd_motu *motu, u32 data,
103 switch (data) {
129 if (data == 0x18) {
151 static int v3_detect_clock_source(struct snd_motu *motu, u32 data,
154 switch (data) {
179 u32 data;
186 data = be32_to_cpu(reg) & V3_CLOCK_SOURCE_MASK;
189 return detect_clock_source_828mk3(motu, data, src);
191 return v3_detect_clock_source(motu, data, src);
198 u32 data;
205 data = be32_to_cpu(reg);
208 data |= V3_FETCH_PCM_FRAMES;
210 data &= ~V3_FETCH_PCM_FRAMES;
212 reg = cpu_to_be32(data);
217 static int detect_packet_formats_828mk3(struct snd_motu *motu, u32 data)
219 if (data & V3_ENABLE_OPT_IN_IFACE_A) {
220 if (data & V3_NO_ADAT_OPT_IN_IFACE_A) {
229 if (data & V3_ENABLE_OPT_IN_IFACE_B) {
230 if (data & V3_NO_ADAT_OPT_IN_IFACE_B) {
239 if (data & V3_ENABLE_OPT_OUT_IFACE_A) {
240 if (data & V3_NO_ADAT_OPT_OUT_IFACE_A) {
249 if (data & V3_ENABLE_OPT_OUT_IFACE_B) {
250 if (data & V3_NO_ADAT_OPT_OUT_IFACE_B) {
265 u32 data;
278 data = be32_to_cpu(reg);
288 return detect_packet_formats_828mk3(motu, data);